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| Datasheet File OCR Text: |
| january 2007 1/108 rev. 4 st7liteusx 8-bit mcu with single voltage flash memory, adc, timers features memories ? 1k bytes single voltage flash program mem- ory with read-out protection, in-circuit and in- application programming (icp and iap). 10k write/erase cycles guaranteed, data retention: 20 years at 55c. ? 128 bytes ram. clock, reset and supply management ? 3-level low voltage supervisor (lvd) and aux- iliary voltage detector (avd) for safe power- on/off procedures ? clock sources: intern al trimmable 8mhz rc oscillator, internal lo w power, low frequency rc oscillator or external clock ? five power saving mo des: halt, auto wake up from halt, active-halt, wait and slow interrupt management ? 11 interrupt vectors plus trap and reset ? 5 external interrupt lines (on 5 vectors) i/o ports ? 5 multifunctional bidirectional i/o lines ? 1 additional output line ? 6 alternate function lines ? 5 high sink outputs 2 timers ? one 8-bit lite timer (lt) with prescaler in- cluding: watchdog, one realtime base and one 8-bit input capture. ? one 12-bit auto-reload timer (at) with output compare function and pwm a/d converter ? 10-bit resolution for 0 to v dd ? 5 input channels instruction set ? 8-bit data manipulation ? 63 basic instructions with illegal opcode de- tection ? 17 main addressing modes ? 8 x 8 unsigned multiply instruction development tools ? full hardware/software development package ? debug module table 1. device summary note 1: for development or tool prototyping purposes only. no t orderable in production quantities. dip8 so8 150? dfn8 features st7ultralite st7liteus2 st7liteus5 program memory - bytes 1k ram (stack) - bytes 128 (64) peripherals lt timer w/ wdg, at timer w/ 1 pwm adc - 10-bit operating supply 2.4v to 3.3v @f cpu =4mhz, 3.3v to 5.5v @f cpu =8mhz cpu frequency up to 8mhz rc operating temperature -40c to +85c / -40c to 125c packages so8 150?, dip8, dfn8, dip16 1) 1
st7liteusx 2/108 st7liteusx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 internal rc oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.3 peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.4 active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.5 auto wake up from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.3 unused i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.6 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 1 st7liteusx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 register & memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 icc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 internal rc oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 reset sequence manager (rsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 non maskable software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.3 peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 system integrity management (si) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.2 slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.3 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.4 active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.5 auto wake up from halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.3 unused i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.6 i/o port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 st7liteusx 3/108 1 10.1 lite timer (lt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2 12-bit autoreload timer (at) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.3 10-bit a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.2 instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.1010-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.2 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . . 95 14.1 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 14.4 st7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 15 known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 15.1 limitations in user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 15.2 limitations in icc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 please pay special attention to the section ?known limitations? on page 104 st7liteusx 4/108 1 introduction the st7ultralite is a member of the st7 mi- crocontroller family. all st7 devices are based on a common industry-standard 8-bit core, featuring an enhanced instruction set. the st7ultralite features flash memory with byte-by-byte in-circuit programming (icp) and in-application prog ramming (iap) capability. under software control, the st7ultralite de- vice can be placed in wait, slow, or halt mode, reducing power consumption when the ap- plication is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. for easy reference, all parametric data are located in section 12 on page 67 . the devices feature an on-chip debug module (dm) to support in-circuit debugging (icd). for a description of the dm registers, refer to the st7 icc protocol reference manual. figure 1. general block diagram 8-bit core alu address and data bus pa3 / reset port a 10-bit adc with watchdog internal clock control ram (128 bytes) pa5:0 (6 bits) v ss v dd power supply 8-mhz rc osc lite timer memory 12-bit auto- reload timer flash 1k byte lvd awu rc osc external clock 1 st7liteusx 5/108 2 pin description figure 2. 8-pin so and dip package pinout figure 3. 8-pin dfn package pinout v dd pa5 (hs) / ain4 / clkin pa3 / reset v ss pa0 (hs) / ain0 / atpwm / iccdata pa2 (hs) / ltic / ain2 pa1 (hs) / ain1 / iccclk pa4 (hs) / ain3 1 2 3 4 8 7 6 5 (hs) : high sink capability eix : associated external interrupt vector ei4 ei3 ei2 ei1 ei0 v dd pa5 (hs) / ain4 / clkin pa3 / reset v ss pa0 (hs) / ain0 / atpwm / iccdata pa2 (hs) / ltic / ain2 pa1 (hs) / ain1 / iccclk pa4 (hs) / ain3 1 2 3 4 8 7 6 5 (hs) : high sink capability eix : associated external interrupt vector ei4 ei3 ei2 ei1 ei0 1 st7liteusx 6/108 pin description (cont?d) figure 4. 16-pin package pinout (for development or tool prototyping purposes only. package not orderable in production quantities.) notes: the differences versus the 8-pin packages are list- ed below: 1. the icc signals (iccclk and iccdata) are mapped on dedicated pins. 2. the reset signal is mapped on a dedicated pin. it is not multiplexed with pa3. 3. pa3 pin is always configured as output. any change on multiplexed io reset control registers (muxcr1 and muxcr2) will have no effect on pa3 functionality. refe r to ?register descrip- tion? on page 24. reserved 1) v dd iccclk nc v ss pa1 (hs) / ain1 pa0 (hs) / ain0 / atpwm reset 1 2 3 4 16 15 14 13 ei4 ei3 ei1 ei0 pa5 (hs) / ain4 / clkin pa4 (hs) / ain3 nc nc iccdata nc pa2 (hs) / ltic / ain2 pa3 5 7 6 8 12 11 10 9 note 1 : must be tied to ground ei2 1 st7liteusx 7/108 pin description (cont?d) legend / abbreviations for table 1 : type: i = input, o = output, s = supply in/output level: c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = high sink (on n-buffer only) port and control configuration: ? input:float = floating, wp u = weak pull-up, int = in- terrupt, ana = analog ? output: od = open drain, pp = push-pull the reset configuration of each pin is shown in bold which is valid as long as the device is in reset state. table 1. device pin description note: 1. after a reset, th e multiplexed pa3/reset pin will act as reset . to configure this pin as output (port a3), write 55h to muxcr0 and aah to muxcr1. for further details, please refer to section 6.4 on page 24 . pin no. pin name type level port / control main function (after reset) alternate function input output input output float wpu int ana od pp 1v dd s main power supply 2 pa5/ain4/ clkin i/o c t hs x ei4 x x x port a5 analog input 4 or external clock input 3 pa4/ain3 i/o c t hs x ei3 x x x port a4 analog input 3 4 pa3/reset 1) o x xx port a3 reset 1) 5 pa2/ain2/ltic i/o c t hs x ei2 x x x port a2 analog input 2 or lite timer input cap- ture 6 pa1/ain1/ iccclk i/o c t hs x ei1 x x x port a1 analog input 1 or in circuit communica- tion clock caution: during normal operation this pin must be pulled-up, internally or ex- ternally (external pull-up of 10k manda- tory in noisy environment). this is to avoid entering icc mode unexpectedly during a reset. in t he application, even if the pin is configured as output, any re- set will put it back in pull-up 7 pa0/ain0/atp- wm/iccdata i/o c t hs x ei0 x x x port a0 analog input 0 or auto-reload timer pwm or in circuit communication data 8v ss s ground 1 st7liteusx 8/108 3 register & memory map as shown in figure 5 , the mcu is capable of ad- dressing 64k bytes of memories and i/o registers. the available memory locations consist of 128 bytes of register locations, 128 bytes of ram and 1 kbytes of user program memory. the ram space includes up to 64 bytes for the stack from 00c0h to 00ffh. the highest address bytes contain the user reset and interrupt vectors. the flash memory contains two sectors (see fig- ure 5 ) mapped in the upper part of the st7 ad- dressing space so the reset and interrupt vectors are located in sector 0 (fe00h-ffffh). the size of flash sector 0 and other device op- tions are configurable by option byte. important: memory locations marked as ?re- served? must never be accessed. accessing a re- seved area can have unpredictable effects on the device. figure 5. memory map note: 1. dee0h, dee1h, dee2h and dee3h addresses are located in a reserved area but are special bytes containing also the rc calibration values which are read-accessible only in user mode. if all the eeprom data or flash space (including the rc calibration valu es locations) has been erased (after the read-out protection removal), then the rc calibration values can still be obtained through these addresses. 0000h ram flash memory (1k) interrupt & reset vectors hw registers 0080h 007fh (see table 2 ) ffe0h ffffh (see table 7 ) 0100h 00ffh short addressing ram (zero page) 64-byte stack 00ffh 0080h 00c0h (128 bytes) fc00h fbffh reserved ffdfh 0.5 kbytes 0.5 kbytes sector 1 sector 0 1k flash ffffh fe00h fdffh fc00h program memory dee0h rccrh0 rccrl0 dee1h see section 6.1 on page 17 rccrh1 rccrl1 dee2h dee3h 1 st7liteusx 9/108 table 2. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a padr paddr paor port a data register port a data direction register port a option register 00h 1) 08h 02h 2) r/w r/w r/w 0003h- 000ah reserved area (8 bytes) 000bh 000ch lite timer ltcsr lticr lite timer control/ status register lite timer input capture register 0xh 00h r/w read only 000dh 000eh 000fh 0010h 0011h 0012h 0013h auto- reload timer atcsr cntrh cntrl atrh atrl pwmcr pwm0csr timer control/status register counter register high counter register low auto-reload register high auto-reload register low pwm output control register pwm 0 control/status register 00h 00h 00h 00h 00h 00h 00h r/w read only read only r/w r/w r/w r/w 0014h to 0016h reserved area (3 bytes) 0017h 0018h auto- reload timer dcr0h dcr0l pwm 0 duty cycle register high pwm 0 duty cycle register low 00h 00h r/w r/w 0019h to 002eh reserved area (22 bytes) 0002fh flash fcsr flash control/status register 00h r/w 0030h to 0033h reserved area (4 bytes) 0034h 0035h 0036h adc adccsr adcdrh adcdrl a/d control status register a/d data register high a/d data register low 00h xxh 00h r/w read only r/w 0037h itc eicr1 external interrupt control register 1 00h r/w 0038h mcc mccsr main clock control/status register 00h r/w 0039h 003ah clock and reset rccr sicsr rc oscillator control register system integrity cont rol/status register ffh 0000 0x00b r/w r/w 003bh to 003ch reserved area (2 bytes) 003dh itc eicr2 external interrupt control register 2 00h r/w 003eh avd avdthcr avd threshold selection register 03h r/w 003fh clock controller ckcntcsr clock controller control/status register 09h r/w 0040h to 0046h reserved area (7 bytes) 1 st7liteusx 10/108 legend: x=undefined, r/w=read/write notes : 1. the contents of the i/o port dr registers are readable only in output configuration. in input configura- tion, the values of the i/o pins are returned instead of the dr register contents. 2. the bits associated with unavailable pins must always keep their reset value. 3. for a description of the dm registers, see the st7 icc protocol reference manual. 0047h 0048h muxio- reset muxcr0 muxcr1 mux io-reset control register 0 mux io-reset control register 1 00h 00h r/w r/w 0049h 004ah awu awupr awucsr awu prescaler register awu control/status register ffh 00h r/w r/w 004bh 004ch 004dh 004eh 004fh 0050h dm 3) dmcr dmsr dmbk1h dmbk1l dmbk2h dmbk2l dm control register dm status register dm breakpoint register 1 high dm breakpoint register 1 low dm breakpoint register 2 high dm breakpoint register 2 low 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w 0051h to 007fh reserved area (47 bytes) address block register label register name reset status remarks 1 st7liteusx 11/108 4 flash program memory 4.1 introduction the st7 single voltage extended flash (xflash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. the xflash devices can be programmed off-board (plugged in a programming tool) or on-board using in-circuit programming or in-application program- ming. the array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 4.2 main features icp (in-circuit programming) iap (in-application programming) ict (in-circuit testing) for downloading and executing user application test patterns in ram sector 0 size configurable by option byte read-out and write protection 4.3 programming modes the st7 can be programmed in three different ways: ? insertion in a programming tool. in this mode, flash sectors 0 and 1 and option byte row can be programmed or erased. ? in-circuit programming. in this mode, flash sectors 0 and 1 and option byte row can be programmed or erased without removing the device from the application board. ? in-application programming. in this mode, sector 1 can be programmed or erased with- out removing the device from the application board and while the application is running. 4.3.1 in-circuit programming (icp) icp uses a protocol called icc (in-circuit commu- nication) which allows an st7 plugged on a print- ed circuit board (pcb) to communicate with an ex- ternal programming device connected via cable. icp is performed in three steps: ? switch the st7 to icc mode (in-circuit commu- nications). this is done by driving a specific sig- nal sequence on the iccclk/data pins while the reset pin is pulled low. when the st7 en- ters icc mode, it fetches a specific reset vec- tor which points to the st7 system memory containing the icc protocol routine. this routine enables the st7 to receive bytes from the icc in- terface. ? download icp driver co de in ram from the ic- cdata pin ? execute icp driver code in ram to program the flash memory depending on the icp driver code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 in application programming (iap) this mode uses an iap driver program previously programmed in sector 0 by the user (in icp mode). this mode is fully contro lled by user software. this allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) iap mode can be used to program any memory ar- eas except sector 0, which is write/erase protect- ed to allow recovery in case errors occur during the programming operation. 1 st7liteusx 12/108 flash program memory (cont?d) 4.4 icc interface icp needs a minimum of 4 and up to 6 pins to be connected to the programming tool. these pins are: ? reset : device reset ?v ss : device power supply ground ? iccclk: icc output serial clock pin (see note 1) ? iccdata: icc input serial data pin ? clkin: main clock input for external source ?v dd : application board power supply (see note 3) figure 6. typical icc interface notes: 1. if the iccclk or iccdata pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programming tool is plugged to the board, even if an icc session is not in progress, the iccclk and iccdata pins are not available for the application. if they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another de- vice forces the signal. refer to the programming tool documentation for recommended resistor val- ues. 2. during the icp session, the programming tool must control the reset pin. this can lead to con- flicts between the programming tool and the appli- cation reset circuit if it drives more than 5ma at high level (push pull output or pull-up resistor<1k). a schottky diode can be used to isolate the appli- cation reset circuit in this case. when using a classical rc network with r>1k or a reset man- agement ic with open drain output and pull-up re- sistor>1k, no additional components are needed. in all cases the user must ensure that no external reset is generated by the application during the icc session. 3. the use of pin 7 of the icc connector depends on the programming tool architecture. this pin must be connected when using most st program- ming tools (it is used to monitor the application power supply). please refer to the programming tool manual. 4. pin 9 has to be connected to the clkin pin of the st7 when icc mode is selected with option bytes disabled (35-pulse icc entry mode). when option bytes are enabled (38-pulse icc entry mode), the internal rc clock (internal rc or awu rc) is forced. if internal rc is selected in the op- tion byte, the internal rc is provided. if awu rc or external clock is selected, the awu rc oscilla- tor is provided. icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable (see note 3) st7 clkin optional see note 1 see note 1 and caution see note 2 application reset source application i/o (see note 4) 3.3k ? (see note 5) 1 st7liteusx 13/108 flash program memory (cont?d) 5. a serial resistor must be connected to icc con- nector pin 6 in order to prevent contention on pa3/ reset pin. contention may occur if a tool forces a state on reset pin while pa3 pin forces the op- posite state in output mode. the resistor value is defined to limit the current below 2ma at 5v. if pa3 is used as output push-pull, then the application must be switched off to allow the tool to take con- trol of the reset pin (pa3). to allow the program- ming tool to drive the reset pin below v il , spe- cial care must also be taken when a pull-up is placed on pa3 for application reasons. caution: during normal operation, iccclk pin must be pulled- up, internally or externally (exter- nal pull-up of 10k mandatory in noisy environ- ment). this is to avoid entering icc mode unex- pectedly during a reset. in the application, even if the pin is configured as output, any reset will put it back in input pull-up. 4.5 memory protection there are two different types of memory protec- tion: read-out protection and write/erase protec- tion which can be applied individually. 4.5.1 read-out protection readout protection, when selected provides a pro- tection against program memory content extrac- tion and against write access to flash memory. even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. program memory is protected. in flash devices, this protection is removed by re- programming the option. in this case, program memory is automatically erased, and the device can be reprogrammed. read-out protection selection depends on the de- vice type: ? in flash devices it is enabled and removed through the fmp_r bit in the option byte. ? in rom devices it is enabled by mask option specified in the option list. 4.5.2 flash write/erase protection write/erase protection, when set, makes it impos- sible to both overwrite and erase program memo- ry. its purpose is to prov ide advanced security to applications and prevent any change being made to the memory content. warning : once set, write/erase protection can never be removed. a write-protected flash device is no longer reprogrammable. write/erase protection is enabled through the fmp_w bit in the option byte. 4.6 related documentation for details on flash programming and icc proto- col, refer to the st7 flash programming refer- ence manual and to the st7 icc protocol refer- ence manual . 4.7 register description flash control/status register (fcsr) read/write reset value: 000 0000 (00h) 1st rass key: 0101 0110 (56h) 2nd rass key: 1010 1110 (aeh) note: this register is reserved for programming using icp, iap or other programming methods. it controls the xflash programming and erasing op- erations. when an epb or anothe r programming tool is used (in socket or icp mode), the rass keys are sent automatically. table 3. flash register map and reset values 70 00000optlatpgm address (hex.) register label 76543210 002fh fcsr reset value 00000 opt 0 lat 0 pgm 0 1 st7liteusx 14/108 5 central processing unit 5.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 5.2 main features 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes two 8-bit index registers 16-bit stack pointer low power modes maskable hardware interrupts non-maskable software interrupt 5.3 cpu registers the six cpu registers shown in figure 7 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a precede in- struction (pre) to indicate that the following in- struction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 7. cpu registers accumulator x index register y index register stack pointer condition code register program counter 70 1c 11hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value 1 st7liteusx 15/108 cpu registers (cont?d) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. bit 4 = h half carry this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested usin g the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 3 = i interrupt mask this bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. 1: interrupts are disabled. this bit is controlled by the rim, sim and iret in- structions and is tested by the jrm and jrnm in- structions. note: interrupts requested while i is set are latched and can be processed when i is cleared. by default an interrupt routine is not interruptible because the i bit is set by hardware at the start of the routine and reset by the iret instruction at the end of the routine. if the i bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. bit 2 = n negative this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (that is, the most signif icant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the ?bit test and branch?, shift and rotate instructions. 70 111hinzc 1 st7liteusx 16/108 cpu registers (cont?d) stack pointer (sp) read/write reset value: 00 ffh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 8 ). since the stack is 64 bytes deep, the 10 most sig- nificant bits are forced by hardware. following an mcu reset, or after a re set stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp5 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 8 . ? when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. ? on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five location s in the stack area. figure 8. . stack manipulation example 15 8 00000000 70 1 1 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 00ffh @ 00c0h stack higher address = 00ffh stack lower address = 00c0h 1 st7liteusx 17/108 6 supply, reset an d clock management the device includes a ran ge of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. main features clock management ? 8 mhz internal rc oscillator (enabled by op- tion byte) ? external clock input (enabled by option byte) reset sequence manager (rsm) system integrity management (si) ? main supply low voltage detection (lvd) with reset generation (enabled by option byte) ? auxiliary voltage detect or (avd) with interrupt capability for monitoring the main supply 6.1 internal rc oscillator adjustment the st7 contains an internal rc oscillator with a specific accuracy for a given device, temperature and voltage. it can be selected as the start up clock through the cksel[1:0] option bits (see sec- tion 14.1 on page 95 ). it must be calibrated to ob- tain the frequency required in the application. this is done by software writ ing a 10-bit calibration val- ue in the rccr (rc control register) and in the bits [6:5] in the sicsr (si control status regis- ter). whenever the microcontroller is reset, the rccr returns to its default value (ffh), i.e. each time the device is reset, the calibration value must be load- ed in the rccr. predefined calibration values are stored in flash memory for 3.3 and 5v v dd supply voltages at 25c, as shown in the following table. 1. dee0h, dee1h, dee2h and dee3h are located in a reserved area but are special bytes containing also the rc calibration values which are read-ac- cessible only in user mode. if all the flash space (including the rc calibration value locations) has been erased (after the read-out protection remov- al), then the rc calibration values can still be ob- tained through these two address. notes: ? in icc mode, the internal rc oscillator is forced as a clock source, regardl ess of the selection in the option byte. refer to note 5 in section 4.4 on page 12 for further details. ? see ?electrical characteristics? on page 67. for more information on the frequency and accuracy of the rc oscillator. ? to improve clock stabilit y and frequency accura- cy, it is recommended to place a decoupling ca- pacitor, typically 100nf, between the v dd and v ss pins as close as possible to the st7 device. caution: if the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. refer to application note an2326 for information on how to calibrate the rc frequency using an ex- ternal reference signal. the st7ultralite also contains an auto wake up rc oscillator. this rc oscillator should be en- abled to enter auto wake-up from halt mode. the auto wake up rc oscillator can also be con- figured as the startup clock through the ck- sel[1:0] option bits (see section 14.1 on page 95 ). this is recommended for applications where very low power consumpt ion is required. switching from one startup clock to another can be done in run mode as follows (see figure 9 ): case 1: switching from internal rc to awu: ? 1. set the rc/awu bit in the ckcntcsr regis- ter to enable the awu rc oscillator ? 2. the rc_flag is cleared and the clock output is at 1. ? 3. wait 3 awu rc cycles till the awu_flag is set ? 4. the switch to the awu clock is made at the positive edge of the awu clock signal ? 5. once the switch is made, the internal rc is stopped case 2: switching from awu rc to internal rc: ? 1. reset the rc/awu bit to enable the internal rc oscillator rccr conditions st7liteus2/ st7liteus5 address rccrh0 v dd =5v t a =25c f rc =8mhz dee0h 1) (cr[9:2] bits) rccrl0 dee1h 1) (cr[1:0] bits) rccrh1 v dd =3.3v t a =25c f rc =8mhz dee2h 1) (cr[9:2] bits) rccrl1 dee3h 1) (cr[1:0] bits) 1 st7liteusx 18/108 supply, reset and clock management (cont?d) ? 2. using a 4-bit counter, wait until 8 internal rc cycles have elapsed. the counter is running on internal rc clock. ? 3. wait till the awu_fl ag is cleared (1awu rc cycle) and the rc_flag is set (2 rc cycles) ? 4. the switch to the internal rc clock is made at the positive edge of the internal rc clock signal ? 5. once the switch is made, the awu rc is stopped notes: 1. when the internal rc is not selected, it is stopped so as to save power consumption. 2. when the internal rc is selected, the awu rc is turned on by hardware when entering auto wake-up from halt mode. 3. when the external clock is selected, the awu rc oscillator is always on. figure 9. clock switching internal rc awu rc set rc/awu poll awu_flag until set internal rc reset rc/awu poll rc_flag until set awu rc 1 st7liteusx 19/108 6.2 register description main clock control/status register (mccsr) read / write reset value: 0000 0000 (00h) bits 7:1 = reserved, must be kept cleared. bit 0 = sms slow mode select this bit is read/write by software and cleared by hardware after a reset. this bit selects the input clock f osc or f osc /32. 0: normal mode (f cpu = f osc 1: slow mode (f cpu = f osc /32) rc control register (rccr) read / write reset value: 1111 1111 (ffh) bits 7:0 = cr[9:2] rc oscillator frequency ad- justment bits these bits, as well as cr[1:0] bits in the sicsr register must be written immediately after reset to adjust the rc oscillator frequency and to obtain the required accuracy. the application can store the correct value for each voltage range in flash memory and write it to this register at start-up. 00h = maximum available frequency ffh = lowest available frequency note: to tune the oscillator, write a series of differ- ent values in the register until the correct frequen- cy is reached. the fastest method is to use a di- chotomy starting with 80h. system integrity (s i) control/status register (sicsr) read/write reset value: 0000 0x00 (0xh) bit 7 = reserved, must be kept cleared. bits 6:5 = cr[1:0] rc oscillator frequency ad- justment bits these bits, as well as cr[9:2] bits in the rccr register must be written immediately after reset to adjust the rc oscillator frequency and to obtain the required accuracy. refer to section 6.1 on page 17 . bits 4:3 = reserved, mu st be kept cleared. bits 2:0 = system integrity bits. refer to section 7.4 system integrity management (si) . 70 0000000sms 70 cr9 cr8 cr7 cr6 cr5 cr4 cr3 cr2 70 0 cr1 cr0 0 0 lvdr f avd f avdi e 1 st7liteusx 20/108 register description (cont?d) avd threshold selection register (avdthcr) read/write reset value: 0000 0011 (03h) bit 7 = reserved, must be kept cleared. bits 6:5 = ck[1:0] internal rc prescaler selection these bits are set by software and cleared by hardware after a reset. these bits select the pres- caler of the internal rc oscillator. see figure 10 on page 21 and the following table and note: table 4. internal rc prescaler selection bits note: if the internal rc is used with a supply oper- ating range below 3.3v, a division ratio of at least 2 must be enabled in the rc prescaler. bits 4:2 = reserved, must be kept cleared. bits 1:0 = avd threshold selection bits. refer to section 7.4 system integrity manage- ment (si) . clock controller control/status register (ckcntcsr) read/write reset value: 0000 1001 (09h) bits 7:4 = reserved, mu st be kept cleared. bit 3 = awu_flag awu selection this bit is set and cleared by hardware 0: no switch from awu to rc requested 1: awu clock activated and temporization com- pleted bit 2 = rc_flag rc selection this bit is set and cleared by hardware 0: no switch from rc to awu requested 1: rc clock activated and temporization complet- ed bit 1 = reserved, must be kept cleared. bit 0 = rc/awu rc/awu selection 0: rc enabled 1: awu enabled (default value) table 5. clock register map and reset values 70 0 ck1 ck0 0 0 0 avd1 avd0 ck1 ck0 f osc 00 f rc 01 f rc/2 10 f rc/4 11 f rc/8 70 0000 awu_ flag rc_ flag 0 rc/ awu address (hex.) register label 7654 3 2 1 0 0038h mccsr reset value 0000 0 0 0 sms 0 0039h rccr reset value cr9 1 cr8 1 cr7 1 cr6 1 cr5 1 cr4 1 cr3 1 cr2 1 003ah sicsr reset value 0 cr1 cr0 0 0 lvdrf x avdf 0 avdie 0 003eh avdthcr reset value 0 ck1 0 ck0 0 00 0 avd1 1 avd2 1 003fh ckcntcsr reset value 0000 awu_flag 1 rc_flag 0 0 rc/awu 1 1 st7liteusx 21/108 supply, reset and clock management (cont?d) figure 10. clock management block diagram mccsr sms peripherals (1ms timebase @ 8 mhz f osc ) f osc /32 f osc f osc f ltimer lite timer counter 13-bit f cpu to cpu and 0 1 cr6 cr9 cr2 cr3 cr4 cr5 cr8 cr7 rccr f osc clkin tunable oscillator internal rc option bits cksel[1:0] /2 divider awu 8mhz 2mhz 1mhz 4mhz prescaler rc 8mhz(f rc ) 33khz clock controller ext clock awu ck rc osc cr1 cr0 sicsr /32 divider f clkin ckcntcsr rc/awu 1 st7liteusx 22/108 6.3 reset sequence manager (rsm) 6.3.1 introduction the reset sequence manager includes three re- set sources as shown in figure 12 : external reset source pulse internal lvd reset (low voltage detection) internal watchdog reset note: a reset can also be triggered following the detection of an illegal opcode or prebyte code. re- fer to figure 12 . these sources act on the reset pin and it is al- ways kept low during the delay phase. the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 11 : active phase depending on the reset source 64 cpu clock cycle delay reset vector fetch caution : when the st7 is unprogrammed or fully erased, the flash is bl ank and the reset vector is not programmed. for this reason, it is recom- mended to keep the reset pin in low state until programming mode is entered, in order to avoid unwanted behavior. the 64 cpu clock cycle delay allows the oscillator to stabilise and ensures th at recovery has taken place from the reset state. the reset vector fetch phase duration is 2 clock cycles. figure 11. reset sequence phases figure 12. reset block diagram reset active phase internal reset 64 clock cycles fetch vector reset r on v dd internal reset pulse generator filter lvd reset watchdog reset illegal opcode reset 1) note 1 : see ?illegal opcode reset? on page 64. for more details on illegal opcode reset conditions. 1 st7liteusx 23/108 reset sequence manager (cont?d) 6.3.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac- cordance with the input voltage. it can be pulled low by external circuitry to reset the device. see electrical characteristic section for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized (see figure 13 ). this de- tection is asynchronous and therefore the mcu can enter reset state even in halt mode. the reset pin is an asynchronous signal which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris- tics section. 6.3.3 external power-on reset if the lvd is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until v dd is over the minimum level specified for the selected f clkin frequency. a proper reset signal for a slow rising v dd supply can generally be provided by an external rc net- work connected to the reset pin. 6.3.4 internal low voltage detector (lvd) reset two different reset sequences caused by the in- ternal lvd circuitry can be distinguished: power-on reset voltage drop reset the device reset pin acts as an output that is pulled low when v dd st7liteusx 25/108 7 interrupts the st7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in table 7, ?interrupt mapping,? on page 26 and a non-maskable software interrupt (trap). the interrupt processing flowchart is shown in fig- ure 14 . the maskable interrupts must be enabled by clearing the i bit in order to be serviced. however, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). note: after reset, all interrupts are disabled. when an interrupt has to be serviced: ? normal processing is suspended at the end of the current instruction execution. ? the pc, x, a and cc registers are saved onto the stack. ? the i bit of the cc register is set to prevent addi- tional interrupts. ? the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the interrupt mapping table for vector address- es). the interrupt service routine should finish with the iret instruction which caus es the contents of the saved registers to be recovered from the stack. note: as a consequence of the iret instruction, the i bit is cleared and the main program resumes. priority management by default, a servicing interrupt cannot be inter- rupted because the i bit is set by hardware enter- ing in interrupt routine. in the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the interrupt map- ping table). interrupts and low power mode all interrupts allow the processor to leave the wait low power mode. only external and specifi- cally mentioned interrupts allow the processor to leave the halt low power mode (refer to the ?exit from halt? column in the interrupt mapping ta- ble). 7.1 non maskable software interrupt this interrupt is entered when the trap instruc- tion is executed regardless of the state of the i bit. it is serviced according to the flowchart in figure 14 . 7.2 external interrupts external interrupt vectors can be loaded into the pc register if the corresponding external interrupt occurred and if the i bit is cleared. these interrupts allow the processor to le ave the halt low power mode. the external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). an external interrupt tr iggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. caution: the type of sensitivity defined in the mis- cellaneous or interrupt register (if available) ap- plies to the ei source. in case of a nanded source (as described in the i/o ports section), a low level on an i/o pin, configured as input with interrupt, masks the interrupt request even in case of rising- edge sensitivity. 7.3 peripheral interrupts different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: ? the i bit of the cc register is cleared. ? the corresponding enable bit is set in the control register. if any of these two conditions is false, the interrupt is latched and thus remains pending. clearing an interrupt request is done by: ? writing ?0? to the corresponding bit in the status register or ? access to the status register while the flag is set followed by a read or write of an associated reg- ister. note : the clearing sequence resets the internal latch. a pending interrupt (that is, waiting for being enabled) will therefore be lost if the clear se- quence is executed. 1 st7liteusx 26/108 interrupts (cont?d) figure 14. interrupt processing flowchart table 7. interrupt mapping notes: 1. this interrupt exits the mcu from ?auto wake-up from halt? mode only. 2. this interrupt exits the mcu from ?wait? and ?active- halt? modes only. moreover, is4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in halt and awufh mode 3. these interrupts exit the mcu from ?active-halt? mode only. n source block description register label priority order exit from halt address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 awu auto wakeup interrupt awucsr yes 1) fffah-fffbh 1 ei0 external interrupt 0 n/a yes fff8h-fff9h 2 ei1 external interrupt 1 fff6h-fff7h 3 ei2 external interrupt 2 fff4h-fff5h 4 not used no fff2h-fff3h 5 ei3 external interrupt 3 yes fff0h-fff1h 6 2) ei4 2) external interrupt 4 2) no 2) ffeeh-ffefh 7 si avd interrupt sicsr no ffech-ffedh 8 at timer at timer output compare interrupt pwmxcsr or atcsr no ffeah-ffebh 9 at timer overflow interrupt atcsr yes 3) ffe8h-ffe9h 10 lite timer lite timer input capture interrupt ltcsr no ffe6h-ffe7h 11 lite timer rtc1 interrupt ltcsr yes 3) ffe4h-ffe5h 12 not used no ffe2h-ffe3h 13 not used no ffe0h-ffe1h i bit set? y n iret? y n from reset load pc from interrupt vector stack pc, x, a, cc set i bit fetch next instruction execute instruction this clears i bit by default restore pc, x, a, cc from stack interrupt y n pending? 1 st7liteusx 27/108 interrupts (cont?d) external interrupt control register 1 (eicr1) read/write reset value: 0000 0000 (00h) bits 7:6 = reserved bits 5:4 = is2[1:0] ei2 sensitivity these bits define the interrupt sensitivity for ei2 according to table 8 . bits 3:2 = is1[1:0] ei1 sensitivity these bits define the interrupt sensitivity for ei1 according to table 8 . bits 1:0 = is0[1:0] ei0 sensitivity these bits define the interrupt sensitivity for ei0 according to table 8 . notes: 1. these 8 bits can be written only when the i bit in the cc register is set. 2. changing the sensitivity of a particular external interrupt clears this pending interrupt. this can be used to clear unwanted pending interrupts. refer to section ?external interrupt function? on page 41. external interrupt control register 2 (eicr2) read/write reset value: 0000 0000 (00h) bits 7:4 = reserved bits 3:2 = is4[1:0] ei4 sensitivity these bits define the interrupt sensitivity for ei1 according to table 8 . bits 1:0 = is3[1:0] ei3 sensitivity these bits define the interrupt sensitivity for ei0 according to table 8 . notes: 1. these 8 bits can be written only when the i bit in the cc register is set. 2. changing the sensitivity of a particular external interrupt clears this pending interrupt. this can be used to clear unwanted pending interrupts. refer to section ?external interrupt function? on page 41. 3. is4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in halt and awufh modes. table 8. interrupt sensitivity bits 70 0 0 is21 is20 is11 is10 is01 is00 70 0000is41is40is31is30 isx1 isx0 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge 1 st7liteusx 28/108 7.4 system integrity management (si) the system integrity management block contains the low voltage detector (lvd) and auxiliary volt- age detector (avd) functions. it is managed by the sicsr register. note: a reset can also be triggered following the detection of an illegal opcode or prebyte code. re- fer to ?illegal opcode reset? on page 64 for further details. 7.4.1 low voltage detector (lvd) the low voltage detector function (lvd) gener- ates a static reset when the v dd supply voltage is below a v it-(lvd) reference value. this means that it secures the power-up as well as the power-down keeping the st7 in reset. the v it-(lvd) reference value for a voltage drop is lower than the v it+(lvd) reference value for power- on in order to avoid a parasitic reset when the mcu starts running and sinks current on the sup- ply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: ?v it+(lvd) when v dd is rising ?v it-(lvd) when v dd is falling the lvd function is illustrated in figure 15 . the voltage threshold can be configured by option byte to be low, medium or high. see section 14.1 on page 95 . provided the minimum v dd value (guaranteed for the oscillator frequency) is above v it-(lvd) , the mcu can only be in two modes: ? under full software control ? in static safe reset in these conditions, secure operation is always en- sured for the application without the need for ex- ternal reset hardware. during a low voltage de tector reset, the reset pin is held low, thus permitting the mcu to reset other devices. notes : use of lvd with capacitive power supply: with this type of power supply, if power cuts occur in the ap- plication, it is recommended to pull v dd down to 0v to ensure optimum restart conditions. refer to circuit example in figure 63 on page 87 and note 4. the lvd is an optional function which can be se- lected by option byte. see section 14.1 on page 95 . it allows the device to be used without any ex- ternal reset circuitry. if the lvd is disabled, an external circuitry must be used to ensure a proper power-on reset. it is recommended to make sure that the v dd sup- ply voltage rises monotonously when the device is exiting from reset, to ensure the application func- tions properly. make sure the right combination of lvd and avd thresholds is used as lvd and avd levels are not correlated. refer to section 12.3.2 on page 70 and section 12.3.3 on page 70 for more details. caution: if an lvd reset occurs after a watchdog reset has occurred, the lvd will take priority and will clear the watchdog flag. figure 15. low voltage detector vs reset v dd v it+ (lvd) reset v it- (lvd) v hys 1 st7liteusx 29/108 system integrity management (cont?d) figure 16. reset and supply management block diagram 7.4.2 auxiliary voltage detector (avd) the voltage detector function (avd) is based on an analog comparison between a v it-(avd) and v it+(avd) reference value and the v dd main sup- ply voltage (v avd ). the v it-(avd) reference value for falling voltage is lower than the v it+(avd) refer- ence value for rising voltage in order to avoid par- asitic detection (hysteresis). the output of the avd comparator is directly read- able by the application software through a real time status bit (avdf) in the sicsr register. this bit is read only. 7.4.2.1 monitoring the v dd main supply. the avd threshold is selected by the avd[1:0] bits in the avdthcr register. if the avd interrupt is enabled, an interrupt is gen- erated when the voltage crosses the v it+(avd) or v it-(avd) threshold (avdf bit is set). in the case of a drop in voltage, the avd interrupt acts as an early warning, allowing software to shut down safely before the lvd resets the microcon- troller. see figure 17 . the interrupt on the rising edge is used to inform the application that the v dd warning state is over note : make sure the right combination of lvd and avd thresholds is used as lvd and avd levels are not correlated. refer to section 12.3.2 on page 70 and section 12.3.3 on page 70 for more details. low voltage detector (lvd) auxiliary voltage detector (avd) reset v ss v dd reset sequence manager (rsm) avd interrupt request system integrity management watchdog sicsr timer (wdg) avd avd lvd rf ie 0 f 0 status flag 1 1 7 0 0 1 st7liteusx 30/108 system integrity management (cont?d) figure 17. using the avd to monitor v dd 7.4.3 low power modes 7.4.3.1 interrupts the avd interrupt event generates an interrupt if the corresponding enable control bit (avdie) is set and the interrupt mask in the cc register is re- set (rim instruction). v dd v it+(avd) v it-(avd) avdf bit 01 reset if avdie bit = 1 v hyst avd interrupt request interrupt cleared by v it+(lvd) v it-(lvd) lvd reset early warning interrupt (power has dropped, mcu not not yet in reset) 0 1 hardware interrupt cleared by reset mode description wait no effect on si. avd interrupts cause the device to exit from wait mode. halt the sicsr register is frozen. the avd remains active but the avd inter- rupt cannot be used to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt avd event avdf avdie yes no 1 st7liteusx 31/108 system integrity management (cont?d) 7.4.4 register description system integrity (si) control/status register (sicsr) read/write reset value: 0000 0x00 (0xh) bit 7 = reserved, must be kept cleared. bits 6:5 = cr[1:0] rc oscillator frequency ad- justment bits these bits, as well as cr[9:2] bits in the rccr register must be written immediately after reset to adjust the rc oscillator frequency and to obtain the required accuracy. refer to section 6.1 on page 17 . bits 4:3 = reserved, must be kept cleared. bit 2 = lvdrf lvd reset flag this bit indicates that the last reset was generat- ed by the lvd block. it is set by hardware (lvd re- set) and cleared when read. see wdgrf flag de- scription in section 10.1 for more details. when the lvd is disabled by option byte, the lvdrf bit value is undefined. note: if the selected clock source is one of the two inter- nal ones, and if v dd remains below the selected lvd threshold during less than t awu (33us typ.), the lvdrf flag cannot be set even if the device is reset by the lvd. if the selected clock source is the external clock (clkin), the flag is never set if the reset occurs during halt mode. in run mode the flag is set only if f clkin is greater than 10mhz. bit 1 = avdf voltage detector flag this read-only bit is set and cleared by hardware. if the avdie bit is set, an interrupt request is gen- erated when the avdf bit is set. refer to figure 17 for additional details 0: v dd over avd threshold 1: v dd under avd threshold bit 0 = avdie voltage detector interrupt enable this bit is set and cleared by software. it enables an interrupt to be generated when the avdf flag is set. the pending interrupt information is automati- cally cleared when software enters the avd inter- rupt routine. 0: avd interrupt disabled 1: avd interrupt enabled avd threshold selection register (avdthcr) read/write reset value: 0000 0011 (03h) bit 7 = reserved, must be kept cleared. bits 6:5 = ck[1:0] internal rc pre scaler selection refer to section 6.1 internal rc oscillator adjustment on page 17 . bits 4:2 = reserved, mu st be kept cleared. bits 1:0 = avd[1:0] avd threshold selection these bits are set and cleared by software and set by hardware after a reset. they select the avd threshold. table 9. avd threshold selection bits application notes the lvdrf flag is not cleared when another re- set type occurs (external or watchdog), the lvdrf flag remains set to keep trace of the origi- nal failure. in this case, a watchdog reset can be detected by software while an external reset can not. 70 0 cr1 cr0 0 0 lvdrf avdf avdie 70 0 ck1 ck0 0 0 0 avd1 avd0 avd1 avd0 functionality 0 0 low 0 1 medium 10 high 1 1 avd off 1 st7liteusx 32/108 register description (cont?d) table 10. system integrity register map and reset values address (hex.) register label 76543210 003ah sicsr reset value 01100 lvdrf x avdf 0 avdie 0 003eh avdthcr reset value 0 ck1 0 ck0 0 000 avd1 1 avd2 1 1 st7liteusx 33/108 8 power saving modes 8.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the st7 (see figure 18 ): slow wait (and slow-wait) active halt auto wake up from halt (awufh) halt after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency (f osc ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by callin g the specific st7 software instruction whose action depends on the oscillator status. figure 18. power saving mode transitions 8.2 slow mode this mode has two targets: ? to reduce power consumption by decreasing the internal clock in the device, ? to adapt the internal clock frequency (f cpu ) to the available supply voltage. slow mode is controlled by the sms bit in the mccsr register which enables or disables slow mode. in this mode, the oscillato r frequency is divided by 32. the cpu and peripherals are clocked at this lower frequency. notes : slow-wait mode is activated when entering wait mode while the devi ce is already in slow mode. figure 19. slow mode clock transition power consumption wait slow run active halt high low slow wait halt sms f cpu normal run mode request f osc f osc /32 f osc 1 st7liteusx 34/108 power saving modes (cont?d) 8.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the ?wfi? instruction. all peripherals remain active. during wait mode, the i bit of the cc register is cleared, to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the pro- gram counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wa it mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 20 . figure 20. wait mode flow-chart note: 1. before servicing an inte rrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. wfi instruction reset interrupt y n n y cpu oscillator peripherals ibit on on 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off 0 on cpu oscillator peripherals ibit on on x 1) on 64 cpu clock cycle delay 1 st7liteusx 35/108 power saving modes (cont?d) 8.4 active-halt and halt modes active-halt and halt modes are the two low- est power consumption modes of the mcu. they are both entered by executing the ?halt? instruc- tion. the decision to enter either in active-halt or halt mode is given by the ltcsr/atcsr reg- ister status as shown in the following table:. 8.4.1 active-halt mode active-halt mode is the lowest power con- sumption mode of the mcu with a real time clock available. it is entered by executing the ?halt? in- struction when active halt mode is enabled. the mcu can exit active-halt mode on recep- tion of a lite timer / at timer interrupt or a re- set. ? when exiting active-halt mode by means of a reset, a 64 cpu cycle delay occurs. after the start up delay, the cpu resumes operation by fetching the reset vector which woke it up (see figure 22 ). ? when exiting active-halt mode by means of an interrupt, the cpu immediately resumes oper- ation by servicing the inte rrupt vector which woke it up (see figure 22 ). when entering active-halt mode, the i bit in the cc register is cleared to enable interrupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in active-halt mode, on ly the main oscillator and the selected timer counter (lt/at) are running to keep a wake-up time base. all other peripherals are not clocked except those which get their clock supply from another clock generator (such as ex- ternal or auxilia ry oscillator). caution: as soon as active-halt is enabled, executing a halt instruction while the watchdog is active does not generate a reset if the wdghalt bit is reset. this means that the device cannot spend more than a defined delay in this power saving mode. figure 21. active-halt timing overview figure 22. active-halt mode flow-chart notes: 1. this delay occurs only if the mcu exits active- halt mode by means of a reset. 2. peripherals clocked with an external clock source can still be active. 3. only the lite timer rtc and at timer interrupts can exit the mcu from active-halt mode. 4. before servicing an inte rrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. ltcsr tbie bit atcsr ovfie bit atcsr ck1 bit atcsr ck0 bit meaning 0xx0 active-halt mode disabled 00xx 0111 1xxx active-halt mode enabled x101 halt run run 64 cpu cycle delay 1) reset or interrupt halt instruction fetch vector active [active halt enabled] halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) ibit on off 0 off fetch reset vector or service interrupt cpu oscillator peripherals 2) ibit on off x 4) on cpu oscillator peripherals ibits on on x 4) on 64 cpu clock cycle delay (active halt enabled) 1 st7liteusx 36/108 power saving modes (cont?d) 8.4.2 halt mode the halt mode is the lo west power consumption mode of the mcu. it is entered by executing the ?halt? instruction when ac tive halt mode is disa- bled. the mcu can exit halt mode on reception of ei- ther a specific interrupt (see table 7, ?interrupt mapping,? on page 26) or a reset. when exiting halt mode by means of a reset or an interrupt, the main oscillator is im mediately turned on and the 64 cpu cycle delay is used to stabilize it. after the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vec- tor which woke it up (see figure 24 ). when entering halt mode, the i bit in the cc reg- ister is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes immedi- ately. in halt mode, the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla- tor). the compatibility of wa tchdog operation with halt mode is configured by the ?wdghalt? op- tion bit of the option byte. the halt instruction when executed while the watchdog system is en- abled, can generate a watchdog reset (see sec- tion 14.1 on page 95 for more details). figure 23. halt timing overview note: 1. a reset pulse of at least 42s must be applied when exiting from halt mode. figure 24. halt mode flow-chart notes: 1. wdghalt is an option bit. see option byte sec- tion for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific inte rrupts can exit the mcu from halt mode (such as external interrupt). re- fer to table 7, ?interrupt mapping,? on page 26 for more details. 4. before servicing an inte rrupt, the cc register is pushed on the stack. the i bit of the cc register is set during the interrupt routine and cleared when the cc register is popped. 5. the cpu clock must be switched to 1mhz (rc/8) or awu rc before entering halt mode. halt run run 64 cpu cycle delay reset or interrupt halt instruction fetch vector [ active halt disabled ] halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) ibit off off 0 off fetch reset vector or service interrupt cpu oscillator peripherals ibit on off x 4) on cpu oscillator peripherals ibits on on x 4) on 64 cpu clock cycle delay 5) watchdog enable disable wdghalt 1) 0 watchdog reset 1 (active halt disabled) 1 st7liteusx 37/108 power saving modes (cont?d) 8.4.2.1 halt mode recommendations ? make sure that an external event is available to wake up the microcontroller from halt mode. ? when using an external interrupt to wake up the microcontroller, reinitia lize the corresponding i/o as ?input pull-up with interrupt? before executing the halt instruction. the main reason for this is that the i/o may be wrongly configured due to ex- ternal interference or by an unforeseen logical condition. ? for the same reason, reinitialize the level sensi- tiveness of each external interrupt as a precau- tionary measure. ? the opcode for the halt instruction is 0x8e. to avoid an unexpected halt instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8e from memo- ry. for example, avoid defining a constant in rom with the value 0x8e. ? as the halt instruction clears the i bit in the cc register to allow interrupts, the user may choose to clear all pending interrupt bits before execut- ing the halt instruction. this avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt). 8.5 auto wake up from halt mode auto wake up from halt (awufh) mode is simi- lar to halt mode with the ad dition of a specific in- ternal rc oscillator for wake-up (auto wake-up from halt oscillator) whic h replaces the main clock which was active before entering halt mode. compared to active-halt mode, awufh has lower power consumption (the main clock is not kept running), but there is no accurate realtime clock available. it is entered by executing the halt instruction when the awuen bit in the awucsr register has been set. figure 25. awufh mode block diagram as soon as halt mode is entered, and if the awuen bit has been set in the awucsr register, the awu rc oscillator provides a clock signal (f awu_rc ). its frequency is divided by a fixed divid- er and a programmable prescaler controlled by the awupr register. the output of this prescaler pro- vides the delay time. when the delay has elapsed, the following actions are performed: ? the awuf flag is set by hardware, ? an interrupt wakes-up t he mcu from halt mode, ? the main oscillator is immediately turned on and the 64 cpu cycle delay is used to stabilize it. after this start-up delay, the cpu resumes opera- tion by servicing the awufh interrupt. the awu flag and its associated interrupt are cleared by software reading the awucsr register. to compensate for any frequency dispersion of the awu rc oscillator, it can be calibrated by measuring the clock frequency f awu_rc and then calculating the right prescaler value. measurement mode is enabled by setting the awum bit in the awucsr register in run mode. this connects f awu_rc to the input capture of the 8-bit lite timer, allowing the f awu_rc to be measured using the main oscillator clock as a reference timebase. awu rc awufh f awu_rc awufh (ei0 source) oscillator prescaler/1 .. 255 interrupt /64 divider to 8-bit timer input capture 1 st7liteusx 38/108 power saving modes (cont?d) similarities with halt mode the following awufh mode behaviour is the same as normal halt mode: ? the mcu can exit awufh mode by means of any interrupt with exit from halt capability or a re- set (see section 8.4 active-halt and halt modes ). ? when entering awufh mode, the i bit in the cc register is forced to 0 to enable interrupts. there- fore, if an interrupt is pending, the mcu wakes up immediately. ? in awufh mode, the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. none of the peripherals are clocked except those which get their clock supply from another clock generator (such as an exte rnal or auxiliary oscil- lator like the awu oscillator). ? the compatibility of wa tchdog operation with awufh mode is configured by the wdghalt option bit in the option byte. depending on this setting, the halt instruction when executed while the watchdog system is enabled, can gen- erate a watchdog reset. figure 26. awuf halt timing diagram awufh interrupt f cpu run mode halt mode 64 t cpu run mode f awu_rc clear by software t awu 1 st7liteusx 39/108 figure 27. awufh mode flow-chart notes: 1. wdghalt is an option bit. see option byte sec- tion for more details. 2. peripheral clocked with an external clock source can still be active. 3. only an awufh interrup t and some specific in- terrupts can exit the mcu from halt mode (such as external interrupt). refer to table 7, ?interrupt mapping,? on page 26 for more details. 4. before servicing an inte rrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg- ister are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. reset interrupt 3) y n n y cpu main osc peripherals 2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu main osc peripherals i[1:0] bits on off xx 4) on cpu main osc peripherals i[1:0] bits on on xx 4) on 64 cpu clock delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 cycle awu rc osc on awu rc osc off awu rc osc off halt instruction (active-halt disabled) (awucsr.awuen=1) 1 st7liteusx 40/108 power saving modes (cont?d) 8.5.1 register description awufh control/status register (awucsr) read/write reset value: 0000 0000 (00h) bits 7:3 = reserved. bit 2= awuf auto wake up flag this bit is set by hardw are when the awu module generates an interrupt and cleared by software on reading awucsr. writing to this bit does not change its value. 0: no awu interrupt occurred 1: awu interrupt occurred bit 1= awum auto wake up measurement this bit enables the aw u rc oscillator and con- nects its output to the input capture of the 8-bit lite timer. this allows the timer to be used to measure the awu rc oscillator dispersion and then com- pensate this dispersion by providing the right value in the awupre register. 0: measurement disabled 1: measurement enabled bit 0 = awuen auto wake up fr om halt enabled this bit enables the auto wake up from halt fea- ture: once halt mode is entered, the awufh wakes up the microcontroller after a time delay de- pendent on the awu prescaler value. it is set and cleared by software. 0: awufh (auto wake up from halt) mode disa- bled 1: awufh (auto wake up from halt) mode ena- bled note: whatever the clock source, this bit should be set to enable the awufh mode once the halt in- struction has been executed. awufh prescaler register (awupr) read/write reset value: 1111 1111 (ffh) bits 7:0= awupr[7:0] auto wake up prescaler these 8 bits define the awupr dividing factor (as explained below: in awu mode, the period that the mcu stays in halt mode (t awu in figure 26 on page 38 ) is de- fined by this prescaler register can be programmed to modify the time that the mcu stays in halt mode before waking up automatically. note: if 00h is written to awupr, depending on the product, an interrupt is generated immediately after a halt instruction, or the awupr remains unchanged. table 11. awu register map and reset values 70 00000 awu f awu m awu en 70 awu pr7 awu pr6 awu pr5 awu pr4 awu pr3 awu pr2 awu pr1 awu pr0 awupr[7:0 ] dividing factor 00h forbidden 01h 1 ... ... feh 254 ffh 255 t awu 64 awupr 1 f awurc ------------------------- -t rcstrt + = address (hex.) register label 76543210 0049h awupr reset value awupr7 1 awupr6 1 awupr5 1 awupr4 1 awupr3 1 awupr2 1 awupr1 1 awupr0 1 004ah awucsr reset value 00000awufawumawuen 1 st7liteusx 41/108 9 i/o ports 9.1 introduction the i/o port offers different functional modes: ? transfer of data through digital inputs and outputs and for specific pins: ? external interrupt generation ? alternate signal input/output for the on-chip pe- ripherals. an i/o port contains up to 6 pins. each pin (except pa3/reset) can be pr ogrammed in dependently as digital input (with or without interrupt genera- tion) or digital output. 9.2 functional description each port has 2 main registers: ? data register (dr) ? data direction register (ddr) and one optional register: ? option register (or) each i/o pin may be programmed using the corre- sponding register bits in the ddr and or regis- ters: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not pro- vide this register refer to the i/o port implementa- tion section). the generic i/o block diagram is shown in figure 28 9.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. notes : 1. writing the dr register modifies the latch value but does not affect the pin status. 2. pa3 cannot be configured as input. 9.2.1.1 external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external inter- rupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the eicr register. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see pinout description and interrupt section). if several i/o interrupt pins on the same interrupt vector are selected simulta- neously, they are logically combined. for this rea- son if one of the interrupt pins is tied low, it may mask the others. external interrupts are hardware interrupts. fetch- ing the corresponding interrupt vector automatical- ly clears the request latch. changing the sensitivity of a particular external interrupt clears this pending interrupt. this can be used to clear unwanted pending interrupts. spurious interrupts when enabling/disabling an external interrupt by setting/resetting the related or register bit, a spu- rious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. this is due to the edge detector input which is switched to '1' when the external interrupt is disa- bled by the or register. to avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before changing the or register bit and configuring the appropriate sensitivity again. caution: in case a pin level change occurs during these operations (asynchro nous signal input), as interrupts are generated according to the current sensitivity, it is advised to disable all interrupts be- fore and to reenable them after the complete pre- vious sequence in order to avoid an external inter- rupt occurring on the unwanted edge. this corresponds to the following steps: 1. to enable an external interrupt: ? set the interrupt mask with the sim instruction (in cases where a pin level change could oc- cur) ? select rising edge ? enable the external interrupt through the or register ? select the desired sensitivity if different from rising edge ? reset the interrupt ma sk with the rim instruc- tion (in cases where a pin level change could occur) 2. to disable an external interrupt: ? set the interrupt mask with the sim instruction sim (in cases where a pin level change could 1 st7liteusx 42/108 occur) ? select falling edge ? disable the external interrupt through the or register ? select rising edge 9.2.2 output modes the output configuration is selected by setting the corresponding ddr register bit. in this case, writ- ing the dr register applies this digital value to the i/o pin through the latch. then reading the dr reg- ister returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. dr register value and output pin status: note: when switching from input to output mode, the dr register has to be written first to drive the correct level on the pin as soon as the port is con- figured as an output. 9.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over the standard i/o programming under the following conditions: ? when the signal is coming from an on-chip pe- ripheral, the i/o pin is automatically configured in output mode (push-pull or open drain according to the peripheral). ? when the signal is going to an on-chip peripher- al, the i/o pin must be configured in floating input mode. in this case, the pin state is also digitally readable by addressing the dr register. notes : ? input pull-up configuration can cause unexpect- ed value at the input of the alternate peripheral input. ? when an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. dr push-pull open-drain 0v ss vss 1v dd floating 1 st7liteusx 43/108 figure 28. i/o port general block diagram table 12. i/o port mode options legend :ni - not implemented off - implemented not activated on - implemented and activated dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external source (ei x ) interrupt polarity selection cmos schmitt trigger register access configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off 1 st7liteusx 44/108 i/o ports (cont?d) table 13. i/o port configurations notes: 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read the alternate function output status. 2. when the i/o port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the dr register content. hardware configuration input 1) open-drain output 2) push-pull output 2) condition pad v dd r pu external interrupt polarity data b u s pull-up interrupt dr register access w r from other pins source (ei x ) selection dr register condition alternate input analog input pad r pu data b u s dr dr register access r/w v dd alternate alternate enable output register pad r pu data b u s dr dr register access r/w v dd alternate alternate enable output register 1 st7liteusx 45/108 i/o ports (cont?d) caution : the alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the select- ed pin to the common analog rail which is connect- ed to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning: the analog input voltage level must be within the limits stated in the absolute maxi- mum ratings. 9.3 unused i/o pins unused i/o pins must be connected to fixed volt- age levels. refer to section 12.8 . 9.4 low power modes 9.5 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and the interrupt mask in the cc register is not active (rim instruction). 9.6 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific feature of the i/o port such as adc in- put or true open drain. switching these i/o ports from one state to anoth- er should be done in a sequence that prevents un- wanted side effects. recommended safe transi- tions are illustrated in figure 29 . other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 29. interrupt i/o port state transitions the i/o port register configurations are summa- rised in the following table: table 14. port configuration note: after reset, to configure pa3 as a general purpose output, the application has to program the muxcr0 and muxcr1 registers. see section 6.4 on page 24 mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupts cause the device to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx yes yes 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or port pin name input (ddr=0) output (ddr=1) or = 0 or = 1 or = 0 or = 1 port a pa0:2, pa4:5 floating pull-up interrupt open drain push-pull pa3 - - open drain push-pull 1 st7liteusx 46/108 i/o ports (cont?d) table 15. i/o port register map and reset values address (hex.) register label 76543210 0000h padr reset value msb 0000000 lsb 0 0001h paddr reset value msb 0000100 lsb 0 0002h paor reset value msb 0000001 lsb 0 1 st7liteusx 47/108 10 on-chip peripherals 10.1 lite timer (lt) 10.1.1 introduction the lite timer can be used for general-purpose timing functions. it is based on a free-running 13- bit upcounter with two software-selectable time- base periods, an 8-bit input capture register and watchdog function. 10.1.2 main features realtime clock ? 13-bit upcounter ? 1 ms or 2 ms timebase period (@ 8 mhz f osc ) ? maskable timebase interrupt input capture ? 8-bit input capture register (lticr) ? maskable interrupt with wakeup from halt mode capability watchdog ? enabled by hardware or software (configura- ble by option byte) ? optional reset on halt instruction (configura- ble by option byte) ? automatically resets the device unless disable bit is refreshed ? software reset (forced watchdog reset) ? watchdog reset status flag figure 30. lite timer block diagram ltcsr watchdog 13-bit upcounter /2 8-bit f ltimer f wdg 8 msb ltic f osc wdgd wdge wdg tbf tbie tb icf icie watchdog reset lttb interrupt request ltic interrupt request lticr input capture register 1 0 1 or 2 ms timebase (@ 8mhz f osc ) to 12-bit at timer f ltimer rf 0 7 1 st7liteusx 48/108 lite timer (cont?d) 10.1.3 functional description the value of the 13-bit counter cannot be read or written by software. after an mcu reset, it starts incrementing from 0 at a frequency of f osc . a counter overflow event occurs when the counter rolls over from 1f39h to 00h. if f osc = 8 mhz, then the time period between two counter overflow events is 1 ms. this peri od can be doubled by set- ting the tb bit in the ltcsr register. when the timer overflows, the tbf bit is set by hardware and an interrupt request is generated if the tbie is set. the tbf bit is cleared by software reading the ltcsr register. 10.1.3.1 watchdog the watchdog is enabled using the wdge bit. the normal watchdog timeout is 2ms (@ fosc = 8 mhz ), after which it then generates a reset. to prevent this watchdog reset occuring, software must set the wdgd bit. the wdgd bit is cleared by hardware after t wdg . this means that software must write to the wdgd bit at regular intervals to prevent a watchdog reset occurring. refer to fig- ure 31 . if the watchdog is not enabled immediately after reset, the first watchd og timeout will be shorter than 2ms, because this period is counted starting from reset. moreover, if a 2ms period has already elapsed after the last mcu reset, the watchdog re- set will take place as soon as the wdge bit is set. for these reasons, it is recommended to enable the watchdog immediately after reset or else to set the wdgd bit before the wgde bit so a watchdog reset will not o ccur for at least 2ms. note: software can use the timebase feature to set the wdgd bit at 1 or 2 ms intervals. a watchdog reset can be forced at any time by setting the wdgrf bit. to generate a forced watchdog reset, first watchdog has to be activated by setting the wdge bit and then the wdgrf bit has to be set. the wdgrf bit also acts as a flag, indicating that the watchdog was the source of the reset. it is au- tomatically cleared after it has been read. caution: when the wdgrf bit is set, software must clear it, otherwise the next time the watchdog is enabled (by hardware or software), the micro- controller will be immediately reset. hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdge bit in the ltcsr is not used. refer to the option byte description in the "device configuration and ordering information" section. using halt mode with the watchdog (option) if the watchdog reset on halt option is not se- lected by option byte, the halt mode can be used when the watchdog is enabled. in this case, the halt in struction stops the oscilla- tor. when the oscillator is stopped, the lite timer stops counting and is no longer able to generate a watchdog reset until the microcontroller receives an external interrupt or a reset. if an external interrupt is received, the wdg re- starts counting after 64 cpu clocks. if a reset is generated, the watchdog is disabled (reset state). if halt mode with watchdog is enabled by option byte (no watchdog reset on halt instruction), it is recommended before executing the halt instruc- tion to refresh the wdg counter, to avoid an unex- pected wdg reset immediately after waking up the microcontroller. figure 31. watchdog timing diagram t wdg f wdg internal watchdog reset wdgd bit software sets wdgd bit hardware clears wdgd bit watchdog reset (2ms @ 8mhz f osc ) 1 st7liteusx 49/108 lite timer (cont?d) input capture the 8-bit input capture register is used to latch the free-running upcounter after a rising or falling edge is detected on the ltic pin. when an input capture occurs, the icf bit is set and the lticr register contains the msb of the free-running upcounter. an interrupt is generated if the icie bit is set. the icf bit is cleared by reading the lticr register. the lticr is a read only register and always con- tains the data from the last input capture. input capture is inhibited if the icf bit is set. 10.1.4 low power modes 10.1.5 interrupts note: the tbf and icf interrupt events are con- nected to separate interrupt vectors (see inter- rupts chapter). they generate an interrupt if the enable bit is set in the ltcsr register and the interrupt mask in the cc register is reset (rim instruction). figure 32. input capture timing diagram mode description wait no effect on lite timer active-halt no effe ct on lite timer halt lite timer stops counting interrupt event event flag enable control bit exit from wait exit from halt exit from active- halt timebase event tbf tbie yes no yes ic event icf icie yes no no 0004h 13-bit counter t 0001h f osc xxh 0002h 0003h 0005h 0006h 0007h 04h ltic pin icf flag lticr register cleared 125ns (@ 8mhz f osc ) f cpu by s/w 07h reading ltic register 1 st7liteusx 50/108 lite timer (cont?d) 10.1.6 register description lite timer control/status register (ltcsr) read / write reset value: 0000 0x00 (0xh) bit 7 = icie interrupt enable. this bit is set and cleared by software. 0: input capture (ic) interrupt disabled 1: input capture (ic) interrupt enabled bit 6 = icf input capture flag. this bit is set by hardware and cleared by software by reading the lticr register. writing to this bit does not change the bit value. 0: no input capture 1: an input capture has occurred note: after an mcu reset, so ftware must initialise the icf bit by reading the lticr register bit 5 = tb timebase period selection. this bit is set and cleared by software. 0: timebase period = t osc * 8000 (1ms @ 8 mhz) 1: timebase period = t osc * 16000 (2ms @ 8 mhz) bit 4 = tbie timebase interrupt enable . this bit is set and cleared by software. 0: timebase (tb) interrupt disabled 1: timebase (tb) interrupt enabled bit 3 = tbf timebase interrupt flag . this bit is set by hardware and cleared by software reading the ltcsr register. writing to this bit has no effect. 0: no counter overflow 1: a counter overflow has occurred bit 2 = wdgrf force reset/ reset status flag this bit is used in two ways: it is set by software to force a watchdog reset. it is set by hardware when a watchdog reset occurs and cleared by hardware or by software. it is cleared by hardware only when an lvd reset occurs. it can be cleared by software after a read access to the ltcsr register. 0: no watchdog reset occurred. 1: force a watchdog reset (write), or, a watchdog reset occurred (read). bit 1 = wdge watchdog enable this bit is set and cleared by software. 0: watchdog disabled 1: watchdog enabled bit 0 = wdgd watchdog reset delay this bit is set by software. it is cleared by hard- ware at the end of each t wdg period. 0: watchdog reset not delayed 1: watchdog reset delayed lite timer input capture register (lticr) read only reset value: 0000 0000 (00h) bits 7:0 = icr[7:0] input capture value these bits are read by software and cleared by hardware after a reset. if the icf bit in the ltcsr is cleared, the value of t he 8-bit up-counter will be captured when a rising or falling edge occurs on the ltic pin. table 16. lite timer register map and reset values 70 icie icf tb tbie tbf wdg r wdge wdg d 70 icr7 icr6 icr5 icr4 icr3 icr2 icr1 icr0 address (hex.)register label76543210 0b ltcsr reset value icie 0 icf 0 tb 0 tbie 0 tbf 0 wdgrf x wdge 0 wdgd 0 0c lticr reset value icr7 0 icr6 0 icr5 0 icr4 0 icr3 0 icr2 0 icr1 0 icr0 0 1 st7liteusx 51/108 10.2 12-bit autoreload timer (at) 10.2.1 introduction the 12-bit autoreload timer can be used for gen- eral-purpose timing functions. it is based on a free- running 12-bit upcounter with a pwm output chan- nel. 10.2.2 main features 12-bit upcounter with 12-bit autoreload register (atr) maskable overflow interrupt pwm signal generator frequency range 2khz-4mhz (@ 8 mhz f cpu ) ? programmable duty-cycle ? polarity control ? maskable compare interrupt output compare function figure 33. block diagram atcsr cmpie ovfie ovf ck0 ck1 0 0 0 12-bit autoreload value 12-bit upcounter cmpf0 bit cmpf0 cmp interrupt request ovf interrupt request f cpu atr pwm generation pol- arity op0 bit pwm0 comp- pare f counter f pwm output control oe0 bit cntr (1 ms timebase f ltimer dcr0h dcr0l update on ovf event preload preload @ 8mhz) 70 on ovf event 0 1 12-bit duty cycle value (shadow) oe0 bit if oe0=1 1 st7liteusx 52/108 12-bit autoreload timer (cont?d) 10.2.3 functional description pwm mode this mode allows a pulse width modulated sig- nals to be generated on the pwm0 output pin with minimum core processing overhead. the pwm0 output signal can be enabled or disabled using the oe0 bit in the pwmcr register. when this bit is set the pwm i/o pin is configured as output push- pull alternate function. note: cmpf0 is available in pwm mode (see pwm0csr description on page 55 ). pwm frequency and duty cycle the pwm signal frequency (f pwm ) is controlled by the counter period and the atr register value. f pwm = f counter / (4096 - atr) following the above formula, if f cpu is 8 mhz, the maximum value of f pwm is 4 mhz (atr register value = 4094), and the minimum value is 2 khz (atr register value = 0). note: the maximum value of atr is 4094 be- cause it must be lower than the dcr value which must be 4095 in this case. at reset, the counter starts counting from 0. software must wr ite the duty cycle value in the dcr0h and dcr0l preload registers. the dcr0h register must be written first. see caution below. when a upcounter overflow occurs (ovf event), the atr value is loaded in the upcounter, the preloaded duty cycle value is transferred to the duty cycle register and the pwm0 signal is set to a high level. when the upcounter matches the dcrx value the pwm0 signals is set to a low level. to obtain a signal on the pwm0 pin, the contents of the dcr0 register must be greater than the con- tents of the atr register. the polarity bit can be used to invert the output signal. the maximum available resolution for the pwm0 duty cycle is: resolution = 1 / (4096 - atr) note : to get the maximum resolution (1/4096), the atr register must be 0. with this maximum reso- lution and assuming that dcr=atr, a 0% or 100% duty cycle can be obtained by changing the polarity . caution: as soon as the dcr0h is written, the compare function is disabled and will start only when the dcr0l value is written. if the dcr0h write occurs just before the compare event, the signal on the pwm output may not be set to a low level. in this case, the dc rx register should be up- dated just after an ovf event. if the dcr and atr values are close, then th e dcrx register shouldbe updated just before an ovf event, in order not to miss a compare event and to have the right signal applied on the pwm output. figure 34. pwm function duty cycle register auto-reload register pwm0 output t 4095 000 with oe0=1 and op0=0 (atr) (dcr0) with oe0=1 and op0=1 counter 1 st7liteusx 53/108 12-bit autoreload timer (cont?d) figure 35. pwm signal example output compare mode to use this function, the oe bit must be 0, other- wise the compare is done with the shadow register instead of the dcrx register. software must then write a 12-bit value in the dcr0h and dcr0l reg- isters. this value will be loaded immediately (with- out waiting for an ovf event). the dcr0h must be written first, the output com- pare function starts only when the dcr0l value is written. when the 12-bit upcounter (cntr) reaches the value stored in the dcr0h and dcr0l registers, the cmpf0 bit in the pwm0csr register is set and an interrupt request is generated if the cmpie bit is set. note: the output compare function is only availa- ble for dcrx values other than 0 (reset value). caution: at each ovf event, the dcrx value is written in a shadow register, even if the dcr0l value has not yet been written (in this case, the shadow register will contain the new dcr0h value and the old dcr0l value), then: ? if oe=1 (pwm mode): the compare is done be- tween the timer counter and the shadow register (and not dcrx) ? if oe=0 (ocmp mode): the compare is done be- tween the timer counter and dcrx. there is no pwm signal. the compare between dcrx or the shadow regis- ter and the timer counter is locked until dcr0l is written. 10.2.4 low power modes 10.2.5 interrupts note 1: the interrupt events are connected to sep- arate interrupt vectors (see interrupts chapter). they generate an interrupt if the enable bit is set in the atcsr register and the interrupt mask in the cc register is reset (rim instruction). note 2: only if ck0=1and ck1=0 counter pwm0 output t with oe0=1 and op0=0 ffdh ffeh fffh ffdh ffeh fffh ffdh ffeh dcr0=ffeh atr= ffdh f counter mode description slow the input frequency is divided by 32 wait no effect on at timer active-halt at timer halted except if ck0=1, ck1=0 and ovfie=1 halt at timer halted interrupt event 1) event flag enable control bit exit from wait exit from halt exit from active- halt overflow event ovf ovfie yes no yes 2) cmp event cmpfx cmpie yes no no 1 st7liteusx 54/108 12-bit autoreload timer (cont?d) 10.2.6 register description timer control status register (atc- sr) read / write reset value: 0000 0000 (00h) bits 7:5 = reserved, must be kept cleared. bits 4:3 = ck[1:0] counter clock selection. these bits are set and cleared by software and cleared by hardware after a reset. they select the clock frequency of the counter. bit 2 = ovf overflow flag. this bit is set by hardware and cleared by software by reading the atcsr register. it indicates the transition of the counter from fffh to atr value. 0: no counter overflow occurred 1: counter overflow occurred caution: when set, the ovf bit stays high for 1 f counter cycle (up to 1ms depending on the clock selection) after it has been cleared by software. bit 1 = ovfie overflow interrupt enable. this bit is read/write by software and cleared by hardware after a reset. 0: ovf interrupt disabled 1: ovf interrupt enabled bit 0 = cmpie compare interrupt enable . this bit is read/write by software and clear by hardware after a reset. it allows to mask the inter- rupt generation when cmpf bit is set. 0: cmpf interrupt disabled 1: cmpf interrupt enabled counter register high (cntrh) read only reset value: 0000 0000 (00h) counter register low (cntrl) read only reset value: 0000 0000 (00h) bits 15:12 = reserved, must be kept cleared. bits 11:0 = cntr[11:0] counter value . this 12-bit register is read by software and cleared by hardware after a reset. the counter is incre- mented continuously as soon as a counter clock is selected. to obtain the 12-bit value, software should read the counter value in two consecutive read operations. as there is no latch, it is recom- mended to read lsb first. in this case, cntrh can be incremented between the two read opera- tions and to have an accurate result when f timer =f cpu , special care must be taken when cn- trl values close to ffh are read. when a counter overflow occurs, the counter re- starts from the value specified in the atr register. 70 0 0 0 ck1 ck0 ovf ovfie cmpie counter clock selection ck1 ck0 off 0 0 f ltimer (1 ms timebase @ 8 mhz) 0 1 f cpu 10 reserved 1 1 15 8 0 0 0 0 cn11 cn10 cn9 cn8 70 cn7 cn6 cn5 cn4 cn3 cn2 cn1 cn0 1 st7liteusx 55/108 12-bit autoreload timer (cont?d) auto reload register (atrh) read / write reset value: 0000 0000 (00h) auto reload register (atrl) read / write reset value: 0000 0000 (00h) bits 15:12 = reserved, must be kept cleared. bits 11:0 = atr[11:0] autoreload register. this is a 12-bit register which is written by soft- ware. the atr register value is automatically loaded into the upcounter when an overflow oc- curs. the register value is used to set the pwm frequency. pwm0 duty cycle register high (dcr0h) read / write reset value: 0000 0000 (00h) pwm0 duty cycle register low (dcr0l) read / write reset value: 0000 0000 (00h) bits 15:12 = reserved, must be kept cleared. bits 11:0 = dcr[11:0] pwmx duty cycle value this 12-bit value is written by software. the high register must be written first. in pwm mode (oe0=1 in the pwmcr register) the dcr[11:0] bits define the duty cycle of the pwm0 output signal (see figure 34 ). in output compare mode, (oe0=0 in the pwmcr register) they define the value to be compared with the 12- bit upcounter value. pwm0 control/status register (pwm0csr) read / write reset value: 0000 0000 (00h) bit 7:2= reserved, must be kept cleared. bit 1 = op0 pwm0 output polarity. this bit is read/write by software and cleared by hardware after a reset. this bit selects the polarity of the pwm0 signal. 0: the pwm0 signal is not inverted. 1: the pwm0 signal is inverted. bit 0 = cmpf0 pwm0 compare flag. this bit is set by hardware and cleared by software by reading the pwm0csr register. it indicates that the upcounter value matches the dcr0 regis- ter value. 0: upcounter value does not match dcr value. 1: upcounter value matches dcr value. 15 8 0 0 0 0 atr11 atr10 atr9 atr8 70 atr7 atr6 atr5 atr4 atr3 atr2 atr1 atr0 15 8 0 0 0 0 dcr11 dcr10 dcr9 dcr8 70 dcr7 dcr6 dcr5 dcr4 dcr3 dcr2 dcr1 dcr0 70 000000op0cmpf0 1 st7liteusx 56/108 12-bit autoreload timer (cont?d) pwm output control register (pwmcr) read/write reset value: 0000 0000 (00h) bits 7:1 = reserved, mu st be kept cleared. bit 0 = oe0 pwm0 output enable . this bit is set and cleared by software. 0: pwm0 output alternate function disabled (i/o pin free for general purpose i/o) 1: pwm0 output enabled table 17. register map and reset values 70 0000000oe0 address (hex.) register label 76543210 0d atcsr reset value 000 ck1 0 ck0 0 ovf 0 ovfie 0 cmpie 0 0e cntrh reset value 0000 cn11 0 cn10 0 cn9 0 cn8 0 0f cntrl reset value cn7 0 cn6 0 cn5 0 cn4 0 cn3 0 cn2 0 cn1 0 cn0 0 10 atrh reset value 0000 atr11 0 atr10 0 atr9 0 atr8 0 11 atrl reset value atr7 0 atr6 0 atr5 0 atr4 0 atr3 0 atr2 0 atr1 0 atr0 0 12 pwmcr reset value 0000000 oe0 0 13 pwm0csr reset value 000000 op 0 cmpf0 0 17 dcr0h reset value 0000 dcr11 0 dcr10 0 dcr9 0 dcr8 0 18 dcr0l reset value dcr7 0 dcr6 0 dcr5 0 dcr4 0 dcr3 0 dcr2 0 dcr1 0 dcr0 0 1 st7liteusx 57/108 10.3 10-bit a/d converter (adc) 10.3.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 10-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 5 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 5 different sources. the result of the conversion is stored in a 10-bit data register. the a/d converter is controlled through a control/status register. 10.3.2 main features 10-bit conversion up to 5 channels with multiplexed input linear successive approximation data register (dr) which contains the results conversion complete status flag on/off bit (to reduce consumption) the block diagram is shown in figure 36 . 10.3.3 functional description 10.3.3.1 analog power supply v dda and v ssa are the high and low level reference voltage pins. in some devices (refer to device pin out description) they are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. figure 36. adc block diagram ch2 ch1 eoc speed adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux d4 d3 d5 d9 d8 d7 d6 d2 adcdrh 3 d1 d0 adcdrl 00 0 0 slow 0 0 r adc c adc hold control f adc f cpu 0 1 1 0 div 2 div 4 slow bit 1 st7liteusx 58/108 10-bit a/d converter (adc) (cont?d) 10.3.3.2 digital a/d conversion result the conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than v dda (high- level voltage reference) then the conversion result is ffh in the adcdrh register and 03h in the ad- cdrl register (without overflow indication). if the input voltage (v ain ) is lower than v ssa (low- level voltage reference) then the conversion result in the adcdrh and adcdrl registers is 00 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdrh and ad- cdrl registers. the accuracy of the conversion is described in the electrical characteristics section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 10.3.3.3 a/d conversion phases the a/d conversion is based on two conversion phases: sample capacitor loading [duration: t sample ] during this phase, the v ain input voltage to be measured is loaded into the c adc sample capacitor. a/d conversion [duration: t hold ] during this phase, the a/d conversion is computed (8 successive approximations cycles) and the c adc sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. the total conversion time: t conv = t sample + t hold while the adc is on, thes e two phases are contin- uously repeated. at the end of each conversion, the sample capaci- tor is kept loaded with the previous measurement load. the advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement. 10.3.3.4 a/d conversion the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the adccsr register: ? select the cs[2:0] bits to assign the analog channel to convert. adc conversion mode in the adccsr register: set the adon bit to enable the a/d converter and to start the conversion. from this time on, the adc performs a continuous conversion of the selected channel. when a conversion is complete: ? the eoc bit is set by hardware. ? the result is in the adcdr registers. a read to the adcdrh resets the eoc bit. to read the 10 bits, perform the following steps: 1. poll eoc bit 2. read adcdrl 3. read adcdrh. this clears eoc automati- cally. to read only 8 bits, perform the following steps: 1. poll eoc bit 2. read adcdrh. this clears eoc automati- cally. 10.3.4 low power modes note: the a/d converter may be disabled by re- setting the adon bit. this feature allows reduced power consumption when no conversion is need- ed and between single shot conversions. 10.3.5 interrupts none. mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d con- verter requires a st abilization time t stab (see electrical characteristics) before accurate conversions can be performed. 1 st7liteusx 59/108 10-bit a/d converter (adc) (cont?d) 10.3.6 register description control/status register (adccsr) read/write (except bit 7 read only) reset value: 0000 0000 (00h) bit 7 = eoc end of conversion this bit is set by hardware. it is cleared by soft- ware reading the adcdrh register. 0: conversion is not complete 1: conversion complete bit 6 = speed adc clock selection this bit is set and cleared by software. it is used together with the slow bit to configure the adc clock speed. refer to the table in the slow bit de- scription. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off 1: a/d converter is switched on bits 4:3 = reserved. must be kept cleared. bits 2:0 = ch[2:0] channel selection these bits are set and cleared by software. they select the analog input to convert. note: a write to the adccsr register (with adon set) aborts the current conversion, resets the eoc bit and starts a new conversion. data register high (adcdrh) read only reset value: 0000 0000 (00h) bits 7:0 = d[9:2] msb of analog converted value data register low (adcdrl) read/write reset value: 0000 0000 (00h) bits 7:5 = reserved. forced by hardware to 0. bit 4 = reserved. forced by hardware to 0. bit 3 = slow slow mode this bit is set and cleared by software. it is used together with the speed bi t to configure the adc clock speed as shown on the table below. bit 2 = reserved. forced by hardware to 0. bits 1:0 = d[1:0] lsb of analog converted value 70 eoc spee d ado n 0 0 ch2 ch1 ch0 channel pin ch2 ch1 ch0 ain0 0 0 0 ain1 0 0 1 ain2 0 1 0 ain3 0 1 1 ain4 1 0 0 70 d9 d8 d7 d6 d5 d4 d3 d2 70 0000slow0d1d0 f adc slow speed f cpu /2 0 0 f cpu 01 f cpu /4 1 x 1 st7liteusx 60/108 table 18. adc register map and reset values address (hex.) register label 76543210 0034h adccsr reset value eoc 0 speed 0 adon 0 0 0 0 0 ch2 0 ch1 0 ch0 0 0035h adcdrh reset value d9 0 d8 0 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 0036h adcdrl reset value 0 0 0 0 0 0 0 0 slow 0 0 0 d1 0 d0 0 1 st7liteusx 61/108 11 instruction set 11.1 st7 addressing modes the st7 core features 17 different addressing modes which can be cla ssified in seven main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two submodes called long and short: ? long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. ? short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 19. st7 addressing mode overview note : 1. at the time the instruction is ex ecuted, the program counter (pc) point s to the instruction following jrxx. addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination/ source pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 (with x register) + 1 (with y register) short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a, ($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10 ],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w ],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc-128/pc+127 1) + 1 relative indirect jrne [$10] pc-128/pc+127 1) 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10] ,#7,skip 00..ff 00..ff byte + 3 1 st7liteusx 62/108 st7 addressing modes (cont?d) 11.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 11.1.2 immediate immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value. 11.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only 1 byte af- ter the opcode, but only allows 00 - ff addressing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 11.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three submodes: indexed (no offset) there is no offset (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 11.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two submodes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low power mode) halt halt oscillator (lowest power mode) ret subroutine return iret interrupt subroutine return sim set interrupt mask rim reset interrupt mask scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations 1 st7liteusx 63/108 st7 addressing modes (cont?d) 11.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two submodes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 20. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 11.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset follows the opcode. relative (indirect) the offset is defined in memory, of which the ad- dress follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic addition/subtrac- tion operations bcp bit compare short instructions only function clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles call, jp call or jump subroutine available relative direct/ indirect instructions function jrxx conditional jump callr call relative 1 st7liteusx 64/108 11.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 ma in groups as illustrated in the following table: using a prebyte the instructions are described with 1 to 4 bytes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the effective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent addressing mode by a y one. pix 92 replace an instruction using direct, di- rect bit or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. it also changes an instruction using x indexed addressing mode to an instruc- tion using indirect x indexed addressing mode. piy 91 replace an instruction using x indirect indexed addressing mode by a y one. 11.2.1 illegal opcode reset in order to provide enhanced robustness to the de- vice against unexpected be havior, a system of ille- gal opcode detection is implemented. if a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. this, com- bined with the watchdog, allows the detection and recovery from an unexpected fault or interference. note: a valid prebyte associated with a valid op- code forming an unauthorized combination does not generate a reset. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret condition code flag modification sim rim scf rcf 1 st7liteusx 65/108 instruction groups (cont?d) mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 0 iret interrupt routine return pop cc, a, x, pc h i n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > 1 st7liteusx 66/108 instruction groups (cont?d) mnemo description function/example dst src h i n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m n z c rrc rotate right true c c => dst => c reg, m n z c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m n z c sll shift left logic c <= dst <= 0 reg, m n z c srl shift right logic 0 => dst => c reg, m 0 z c sra shift right arithmetic dst7 => dst => c reg, m n z c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z 1 st7liteusx 67/108 12 electrical characteristics 12.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 12.1.1 minimum and maximum values unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 12.1.2 typical values unless otherwise specified, typical data are based on t a =25c, v dd =5v (for the 4.5v v dd 5.5v volt- age range), v dd =3.75v (for the 3v v dd 4.5v voltage range) and v dd =2.7v (for the 2.4v v dd 3v voltage range). they are given only as design guidelines and are not tested. 12.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 12.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 37 . figure 37. pin loading conditions 12.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 38 . figure 38. pin input voltage c l st7 pin v in st7 pin 1 st7liteusx 68/108 12.2 absolute ma ximum ratings stresses above those listed as ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 12.2.1 voltage characteristics 12.2.2 current characteristics 12.2.3 thermal characteristics notes: 1. directly connecting the i/o pins to v dd or v ss could damage the device if an unexpect ed change of the i/o configura- tion occurs (for example, due to a co rrupted program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-dow n resistor (typical: 10k ? for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current mu st be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in st7liteusx 70/108 12.3.2 operating condi tions with low voltage detector (lvd) t a = -40 to 125c, unless otherwise specified notes: 1. not tested in production. 2. not tested in production. the v dd rise time rate condition is needed to ens ure a correct device power-on and lvd reset release. when the v dd slope is outside these values, the lvd may not release properly the reset of the mcu. 3. lvd and avd high thresholds must not be selected at the same time. 4. use of lvd with capacitive power supply: with this type of power supply, if power cuts occu r in the application, it is recommended to pull v dd down to 0v to ensure optimum restart conditions. refer to circuit example in figure 62 on page 87 . 12.3.3 auxiliary voltage detector (avd) thresholds t a = -40 to 125c, unless otherwise specified notes : 1. lvd and avd high thresholds must not be selected at the same time. 2. not tested in production, guaranteed by characterization. note : refer to section 7.4.2.1 on page 29 symbol parameter conditions 3) min typ max unit v it+ (lvd) reset release threshold (v dd rise) high threshold med. threshold low threshold 3.50 3.30 2.50 4.00 3.70 2.65 4.50 4.30 3.30 v v it- (lvd) reset generation threshold (v dd fall) high threshold med. threshold low threshold 3.30 3.20 2.40 3.80 3.50 2.70 4.40 4.20 3.20 v hys lvd voltage threshold hysteresis v it+ (lvd) -v it- (lvd) 150 mv vt por v dd rise time rate 2) 4) 20 - s/v i dd(lvd) 1) lvd/avd current consumption v dd = 5v 220 a symbol parameter conditions 1) min 2) typ 2) max 2) unit v it+ (avd) 1=>0 avdf flag toggle threshold (v dd rise) high threshold med. threshold low threshold 3.50 3.30 2.50 4.10 3.90 3.00 4.80 4.60 3.50 v v it- (avd) 0=>1 avdf flag toggle threshold (v dd fall) high threshold med. threshold low threshold 3.40 3.20 2.40 4.00 3.80 2.90 4.70 4.50 3.40 v hys avd voltage threshold hysteresis v it+ (avd) -v it- (avd) 100 mv ? v it- voltage drop between avd flag set and lvd reset activation v dd fall 0.45 v 1 st7liteusx 71/108 operating conditions (cont?d) 12.3.4 voltage drop between avd flag set and lvd reset generation note : 1. not tested in production, guaranteed by characterization. 12.3.5 internal rc oscillator 12.3.5.1 internal rc oscillator calibrated at 5.0v the st7 internal clock can be supplied by an inte rnal rc oscillator (selectable by option byte). notes: 1. see ?internal rc oscillator adjustment? on page 17 2. guaranteed by design. to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nf, between the v dd and v ss pins as close as possible to the st7 device parameter min 1) typ 1) max 1) unit avd med. threshold - avd low. threshold 700 950 1200 mv avd high. threshold - avd low threshold 900 1150 1400 avd high. threshold - avd med. threshold 100 200 300 avd low threshold - lvd low threshold 0 100 300 avd med. threshold - lvd low threshold 800 1000 1300 avd med. threshold - lvd med. threshold 50 200 300 avd high. threshold - lvd low threshold 850 1250 1700 avd high. threshold - lvd med. threshold 200 400 600 symbol parameter conditions min typ max unit f rc internal rc oscillator frequency rccr = ff (reset value), t a =25c,v dd =5v 4.5 mhz rccr = rccr0 1) ,t a =25c,v dd =5v 8 acc rc accuracy of internal rc oscillator with rccr=rccr0 1) t a =25c, v dd =5v -2 +2 % t a =25c, v dd =4.5 to 5.5v -3 +3 % t a =0 to +85c, v dd =5v -3.5 +4.5 % t a =0 to +85c, v dd =4.5 to 5.5v -4 +5 % t a =0 to +125c, v dd =5v -3.5 +6 % t a =0 to +125c, v dd =4.5 to 5.5v -5 +7 % t a =-40c to 0c, v dd =4.5 to 5.5v -6 +5 % i dd(rc) rc oscillator current consumption t a =25c, v dd =5v 900 2) a t su(rc) rc oscillator setup time t a =25c, v dd =5v 4 2) s 1 st7liteusx 72/108 12.3.5.2 internal rc oscillator calibrated at 3.3v the st7 internal clock can be supplied by an inte rnal rc oscillator (selectable by option byte). notes: 1. see ?internal rc oscillator adjustment? on page 17 2. guaranteed by design. figure 40. internal rc osci llator frequency vs. temperature (rccr=rccr0) at v dd = 5.0v figure 41. internal rc osci llator frequency vs. temperature (rccr=rccr1) at v dd = 3.3v symbol parameter conditions min typ max unit f rc internal rc oscillator frequency rccr = ff (reset value), t a =25c,v dd =3.3v 4.4 mhz rccr = rccr1 1 ) ,t a =25c,v dd =3.3v 8 acc rc accuracy of internal rc oscillator with rccr=rccr1 1) t a =25c, v dd =3.3v -2 +2 % t a =25c, v dd =3.0 to 3.6v -4 +4 % t a =0 to +85c, v dd =3.3v -4 +3.5 % t a =0 to +85c, v dd =3.0 to 3.6v -6 +5 % t a =0 to +125c, v dd =3.3v -5.5 +4.5 % t a =0 to +125c, v dd =3.0 to 3.6v -7 +5.5 % t a =-40c to 0c, v dd =3.0 to 3.6v -6 +6 % i dd(rc) rc oscillator current consumption t a =25c, v dd =3.3v 900 2) a t su(rc) rc oscillator setup time t a =25c, v dd =3.3v 4 2) s 7.75 8 8.25 -60 -40 -20 0 20 40 60 80 100 120 140 ta (c) frc (mhz) 4.5v 5.0v 5.5v 7.5 7.75 8 8.25 -60 -40 -20 0 20 40 60 80 100 120 140 ta (c) frc (mhz) 3.0v 3.3v 3.6v 1 st7liteusx 73/108 12.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode for which the clock is stopped). 12.4.1 supply current t a = -40 to +125c unle ss otherwise specified notes: 1. cpu running with memory access, all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driv en by external square wave, lvd disabled. 2. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals in re set state; clock input (clkin) driven by external square wave, lvd disabled. 3. slow mode selected with f cpu based on f osc divided by 32. all i/o pins in i nput mode with a static value at v dd or v ss (no load), all peripherals in reset state; clock input (clkin) driven by external square wave, lvd disabled. 4. slow-wait mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripher als in reset state; clock input (clkin) dr iven by external square wave, lvd disabled. 5. all i/o pins in input mode with a static value at v dd or v ss (no load). data tested in production at v dd max. and f cpu max. 6. this consumption refers to the ha lt period only and not the associated run period which is software dependent. 7. all i/o pins in output mode with a static value at v ss (no load), lvd disabl ed. data based on characterization results, tested in production at v dd max and f cpu max. 8. data based on characteriza tion, not tested in production. symbol parameter conditions typ max unit i dd supply current in run mode 1) v dd =5v f cpu = 4mhz 2.5 5.0 ma f cpu = 8mhz 5.0 9.0 supply current in wait mode 2) f cpu = 4mhz 1.0 2.5 f cpu = 8mhz 1.5 4.0 supply current in slow mode 3) f cpu /32 = 250khz 650 1100 a supply current in slow-wait mode 4) f cpu /32 = 250khz 500 900 supply current in awufh mode 5)6) 40 120 8) supply current in active halt mode 100 250 supply current in halt mode 7) 0.5 3 supply current in run mode 1) v dd =3v f cpu = 4mhz 1.5 4.0 8) ma supply current in wait mode 2) f cpu = 4mhz 0.5 2.5 8) supply current in slow mode 3) f cpu /32 = 250khz 350 700 8) a supply current in slow-wait mode 4) f cpu /32 = 250khz 285 600 8) supply current in awufh mode 5)6) 15 80 8) supply current in active halt mode 70 200 supply current in halt mode 7) 0.25 3 8) 1 st7liteusx 74/108 supply current characteristics (cont?d) figure 42. typical i dd in run mode vs. f cpu figure 43. typical i dd in slow mode vs. f cpu figure 44. typical i dd in wait mode vs. f cpu figure 45. typical i dd in slow-wait mode vs. f cpu figure 46. typical i dd vs. temperature at v dd = 5v and f cpu = 8mhz 0.00 1.00 2.00 3.00 4.00 5.00 6.00 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 vdd [v] idd [ma] 2mhz 4mhz 8mhz 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 vdd [v] idd [ma] 2mhz 4mhz 8mhz 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 vdd [v] idd [ma] 2mhz 4mhz 8mhz 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 vdd [v] idd [ma] 2mhz 4mhz 8mhz 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 -45 25 90 vdd [v] idd [ma] run wait slow slowwait 1 st7liteusx 75/108 12.4.2 on-chip peripherals notes: 1. data based on a differential i dd measurement between reset configurati on (timer stopped) and the timer running in pwm mode at f cpu =8mhz. 2. data based on a differential i dd measurement between reset configuration and continuous a/d conversions with am- plifier off. 3. not tested in production, guaranteed by characterization. symbol parameter conditions typ 3) unit i dd(at) 12-bit auto-reload timer supply current 1) f cpu =4mhz v dd = 3.0v 15 a f cpu =8mhz v dd = 5.0v 30 i dd(adc) adc supply current when converting 2) f adc =2mhz v dd = 3.0v 450 f adc =4mhz v dd = 5.0v 750 1 st7liteusx 76/108 12.5 clock and timing characteristics subject to general operating conditions for v dd , f osc , and t a . 12.5.1 general timings notes: 1. data based on characterization. not tested in production. 2. data based on typical application software. 3. time measured between interrupt ev ent and interrupt vector fetch. ? t c(inst) is the number of t cpu cycles needed to fin- ish the current instruction execution. 12.5.2 auto wakeup rc oscillator note: 1. data guaranteed by design. symbol parameter 1) conditions min typ 2) max unit t c(inst) instruction cycle time f cpu =8mhz 2312t cpu 250 375 1500 ns t v(it) interrupt reaction time 3) t v(it) = ? t c(inst) + 10 f cpu =8mhz 10 22 t cpu 1.25 2.75 s parameter conditions min typ max unit supply voltage range 2.4 5.0 5.5 v operating temperature range -40 25 125 c current consumption 1) without prescaler 2.0 8.0 14.0 a consumption 1) awu rc switched off 0 a output frequency 1) 20 33 60 khz 1 st7liteusx 77/108 12.6 memory characteristics t a = -40c to 125c, unless otherwise specified 12.6.1 ram and hardware registers 12.6.2 flash program memory notes: 1. minimum v dd supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware reg- isters (only in halt mode). guaranteed by construction, not tested in production. 2. up to 32 bytes can be programmed at a time. 3. the data retention time increases when the t a decreases. 4. data based on reliability test results and monitored in production. 5. data based on characterization results, not tested in production. 6. guaranteed by design. not tested in production. 7. design target value pending fu ll product characterization. symbol parameter conditions min typ max unit v rm data retention mode 1) halt mode (or reset) 1.6 v symbol parameter conditions min typ max unit v dd operating voltage for fl ash write/erase 2.4 5.5 v t prog programming time for 1~32 bytes 2) t a =? 40 to +125c 5 10 ms programming time for 1 kbyte t a = +25c 0.16 0.32 s t ret data retention 4) t a = +55c 3) 20 years n rw write erase cycles t a = +25c 10k 7) cycles i dd supply current 6) read / write / erase modes f cpu = 8mhz , v dd = 5.5v 2.6 ma no read/no write mode 100 a power down mode / halt 0 0.1 a 1 st7liteusx 78/108 12.7 emc characteristics susceptibility tests are pe rformed on a sample ba- sis during product characterization. 12.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturba nce occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test confor ms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re- sumed. the test results are given in the table be- low based on the ems levels and classes defined in application note an1709. 12.7.1.1 designing hardened software to avoid noise problems emc characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the manage- ment of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the re- set pin or the oscillator pins for 1 second. to complete these trials, esd stress can be ap- plied directly on the device, over the range of specification values. when unexpected behaviour is detected, the software can be hardened to pre- vent unrecoverable errors occurring (see applica- tion note an1015). symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz, so8 package, conforms to iec 1000-4-2 3b v fftb fast transient voltage bur st limits to be applied through 100pf on v dd and v dd pins to induce a func- tional disturbance v dd = 5v, t a = +25c, f osc = 8mhz, so8 package, conforms to iec 1000-4-4 4b 1 st7liteusx 79/108 emc characteristics (cont?d) 12.7.2 electro magnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emission. this emission test is in line with the norm sae j 1752/ 3 which specifies the board and the loading of each pin. note: 1. data based on characterization results, not tested in production. 12.7.3 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu and dlu) using specific measuremen t methods, the product is stressed in order to determine its performance in terms of electrical sensitiv ity. for more details, re- fer to the application note an1181. 12.7.3.1 electro-static discharge (esd) electro-static discharges (a positive then a nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). one model can be simulated: human body model. this test conforms to the jesd22- a114a/a115a standard. absolute maximum ratings note: 1. data based on characterization re sults, not tested in production. symbol parameter conditions monitored frequency band max vs. [f osc /f cpu ] unit -/8mhz s emi peak level v dd = 5v, t a = +25c, so8 package, conforming to sae j 1752/3 0.1mhz to 30mhz 21 db v 30mhz to 130mhz 23 130mhz to 1ghz 10 sae emi level 3 - symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c > 4000 v 1 st7liteusx 80/108 emc characteristics (cont?d) 12.7.3.2 static and dynamic latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1 000-4-2 and saej1752/3 standards. for more details, refer to the application note an1181. electrical sensitivities note: 1. class description: a class is an stmicroelec tronics internal specificat ion. all its limits are hi gher than the jedec spec- ifications, that means when a device belongs to class a it exceeds the jedec standar d. b class strictly covers all the jedec criteria (int ernational standard). symbol parameter conditions class 1) lu static latch-up class t a = +125c a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25c a 1 st7liteusx 81/108 12.8 i/o port pin characteristics 12.8.1 general characteristics subject to general operating conditions for v dd , f osc , and t a unless otherwise specified. notes: 1. data based on characterization re sults, not tested in production. 2. configuration not recommended, all unused pins must be kept at a fixed voltage: using t he output mode of the i/o for example or an external pull- up or pull-down resistor (see figure 51 ). static peak current value taken at a fixed v in value, based on design simulation and technology characteristics, not tested in production. this value depends on v dd and tem- perature values. 3. the r pu pull-up equivalent resistor is based on a resistive transistor (corresponding i pu current characteristics de- scribed in figure 48 ). 4. to generate an external interrupt, a mini mum pulse width has to be applied on an i/o port pin configured as an external interrupt source. 5. r pu not applicable on pa3 because it is multiplexed on reset pin figure 47. two typical applications with unused i/o pin symbol parameter conditions min typ max unit v il input low level voltage -40c to 125c 0.3xv dd v v ih input high level voltage 0.7 x v dd v hys schmitt trigger voltage hysteresis 1) 400 mv i l input leakage current v ss v in v dd 1 a i s static current consumption in- duced by each floating input pin 2) floating input mode 400 r pu weak pull-up equivalent resistor 3) 5) v in = v ss v dd =5v 80 120 170 k ? v dd =3v 200 1) c io i/o pin capacitance 5 pf t f(io)out output high to low level fall time 1) c l =50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time 1) 25 t w(it)in external interrupt pulse time 4) 1t cpu 10k ? unused i/o port st7xxx 10k ? unused i/o port st7xxx v dd caution : during normal operation th e iccclk pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in this is to avoid entering icc mode unexpectedly during a reset. noisy environment). note : i/o can be left unconnected if it is configured as output (0 or 1) by the software. this has the advantage of greater emc robustness and lower cost. 1 st7liteusx 82/108 i/o port pin characteristics (cont?d) figure 48. typical i pu vs. v dd with v in =v ss l 12.8.2 output driving current subject to general operating conditions for v dd , f cpu , and t a unless otherwise specified. notes: 1. the i io current sunk must always respect t he absolute maximum rating specified in section 12.2.2 and the sum of i io (i/o ports and control pi ns) must not exceed i vss . 2. the i io current sourced must always respect t he absolute maximum rating specified in section 12.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins do not have v oh . 3. not tested in production, based on characterization results. symbol parameter conditions min max unit v ol 1) output low level voltage for pa3/reset standard i/o pin (see figure 51 ) v dd =5v i io =+5ma,t a 125c 1200 mv i io =+2ma,t a 125c 400 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 54 ) i io =+20ma, t a 125c 1300 i io =+8ma,t a 125c 750 v oh 2) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 58 ) i io =-5ma,t a 125c v dd -1500 i io =-2ma,t a 125c v dd -800 v ol 1)3) output low level voltage for pa3/reset standard i/o pin (see figure 50 ) v dd =3v i io =+2ma,t a 125c 250 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 53 ) i io =+2ma,t a 125c 150 i io =+8ma,t a 125c 500 v oh 2)3) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 56 ) i io =-2ma,t a 125c v dd -800 v ol 1)3) output low level voltage for pa3/reset standard i/o pin (see figure 49 ) v dd =2.4v i io =+2ma,t a 125c 500 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 52 ) i io =+2ma,t a 125c 200 i io =+8ma,t a 125c 600 v oh 2)3) output high level voltage for an i/o pin when 4 pins are sourced at same time (see figure 55 ) i io =-2ma,t a 125c v dd -900 0 10 20 30 40 50 60 70 80 90 2 . 4 2 . 8 3. 2 3. 6 4 4. 4 4. 8 5 . 2 5 . 6 6 vdd [v] ipu [ua] -45c 25c 90c 1 st7liteusx 83/108 i/o port pin characteristics (cont?d) figure 49. typical v ol at v dd = 2.4v (standard pins) figure 50. typical v ol at v dd = 3v (standard pins) figure 51. typical v ol at v dd = 5v (standard pins) figure 52. typical v ol at v dd = 2.4v (hs pins) figure 53. typical v ol at v dd = 3v (hs pins) figure 54. typical v ol at v dd = 5v (hs pins) 0 200 400 600 800 1000 0246 iload (ma) vol (mv) at vdd=2.4 v(std) -45c 25c 90c 0 200 400 600 800 1000 0246 iload (ma) vol (mv) at vdd=3 v(std) -45c 25c 90c 0 200 400 600 800 0246 iload (ma) vol (mv) at vdd=5v(std) -45c 25c 90c 0 200 400 600 800 1000 1200 0 2 4 6 8 101214161820 iload[ma] vol [mv] 25c -45c 90c 0 200 400 600 800 1000 1200 02468101214161820 iload[ma] vol [mv] 25c -45c 90c 0 100 200 300 400 500 600 700 800 900 1000 02468101214161820 iload[ma] vol [mv] 25c -45c 90c 1 st7liteusx 84/108 i/o port pin characteristics (cont?d) figure 55. typical v dd -v oh at v dd = 2.4v (hs pins) figure 56. typical v dd -v oh at v dd = 3v (hs pins) figure 57. typical v dd -v oh at v dd = 4v (hs pins) figure 58. typical v dd -v oh at v dd = 5v (hs pins) figure 59. typical v ol vs. v dd (standard i/os) 0 200 400 600 800 1000 1200 0 -2-4-6-8-10-12 iload [ma] vdd-voh [mv] -45c 25c 90c 0 100 200 300 400 500 600 700 800 900 1000 0 -2-4-6-8-10-12 iload [ma] vdd-voh [mv] -45c 25c 90c 0 100 200 300 400 500 600 700 0 -2-4-6-8-10-12 iload [ma] vdd-voh [mv] -45c 25c 90c 0 100 200 300 400 500 600 0-2-4-6-8-10-12 iload [ma] vdd-voh [mv] -45c 25c 90c 0 50 100 150 200 250 300 350 400 450 500 2.4 3 3.4 4 4.4 5 5.4 6 vdd [v} vol [mv] at iload=2ma -45c 25c 90c 1 st7liteusx 85/108 i/o port pin characteristics (cont?d) figure 60. typical v ol vs. v dd (hs pins) figure 61. typical v dd -v oh vs. v dd (hs pins) 0 50 100 150 200 250 300 350 400 450 500 2.4 3 3.4 4 4.4 5 5.4 6 vdd [v] vol [mv] at iload = 8ma -45c 25c 90c 0 100 200 300 400 500 600 700 800 900 2.433.444.455.46 vdd [v] vol [mv] at iload = 12ma -45c 25c 90c 0 20 40 60 80 100 120 140 160 180 2.433.444.455.46 vdd [v] vdd-voh [mv] at iload=2 ma -45c 25c 90c 0 100 200 300 400 500 600 2.433.444.455.46 vdd [v] vdd-voh [mv] at iload = 6ma -45c 25c 90c 1 st7liteusx 86/108 12.9 control pin characteristics 12.9.1 asynchronous reset pin t a = -40c to 125c, unless otherwise specified notes: 1. data based on characterization results, not tested in production. 2. the i io current sunk must always respect t he absolute maximum rating specified in section 12.2.2 on page 68 and the sum of i io (i/o ports and control pins) must not exceed i vss . 3. the r on pull-up equivalent resistor is based on a resistiv e transistor. specified for voltages on reset pin between v ilmax and v dd 4. to guarantee the reset of the device, a mi nimum pulse has to be applied to the r eset pin. all short pulses applied on reset pin with a duration below t h(rstl)in can be ignored. symbol parameter conditions min typ max unit v il input low level voltage v ss - 0.3 0.3xv dd v v ih input high level voltage 0.7xv dd v dd + 0.3 v hys schmitt trigger voltage hysteresis 1) 2v v ol output low level voltage 2) v dd =5v i io =+2ma 400 mv r on pull-up equivalent resistor 3) v in = v ss v dd =5v 30 50 70 k ? v dd =3v 90 1) t w(rstl)out generated reset pulse duration internal reset sources 90 1) s t h(rstl)in external reset pulse hold time 4) 20 s t g(rstl)in filtered glitch duration 200 ns 1 st7liteusx 87/108 control pin characteristics (cont?d) figure 62. reset pin protection when lvd is enabled. 1)2)3)4) figure 63. reset pin protection when lvd is disabled. 1) note 1: ? the reset network protects the device against parasitic resets. ? the output of the external reset circuit must have an open- drain output to drive the st7 reset pad. otherwise the device can be damaged when the st7 generates an internal reset (lvd or watchdog). ? whatever the reset source is (int ernal or external), the user must ensure that the level on the reset pin can go below the v il max. level specified in section 12.9.1 on page 86 . otherwise the reset will not be taken into account internally. ? because the reset circuit is designed to allow the internal reset to be output in the reset pin, the user must en- sure that the current sunk on the reset pin is less than the absolute maximum value specified for i inj(reset) in section 12.2.2 on page 68 . note 2: when the lvd is enabled, it is recommended not to c onnect a pull-up resistor or capacitor. a 10nf pull-down capacitor is required to fi lter noise on the reset line. note 3: in case a capacitive power supply is used, it is recommended to connect a 1m ? pull-down resistor to the reset pin to discharge any residual voltage induc ed by the capacitive effect of the power supply (this will add 5a to the power consumption of the mcu). note 4: tips when using the lvd: ? 1. check that all recommendations related to i ccclk and reset circuit have been applied (see caution in table 1 on page 7 and notes above) ? 2. check that the power supply is properly decoupled (100nf + 10f close to the mcu). refer to an1709 and an2017. if this cannot be done, it is recommended to put a 100nf + 1m ? pull-down on the reset pin. ? 3. the capacitors connected on the reset pin and also the power supply are key to avoi d any start-up marginality. in most cases, steps 1 and 2 above are sufficient for a robust solution. otherwise: replace 10nf pull-down on the reset pin with a 5f to 20f capacitor.? note 5: please refer to ?illegal opcode reset? on page 64 for more details on ill egal opcode reset conditions 0.01 f st72xxx pulse generator filter r on v dd internal reset reset external required 1m ? optional (note 3) watchdog lvd reset illegal opcode 5) 0.01 f external reset circuit user required st72xxx pulse generator filter r on v dd internal reset watchdog illegal opcode 5) 1 st7liteusx 88/108 12.10 10-bit adc characteristics subject to general operating condition for v dd , f osc , and t a unless otherwise specified. notes: 1. unless otherwise specifi ed, typical data are based on t a =25c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. 2. the maximum adc clock frequency allowed within v dd = 2.4v to 2.7v operating range is 1mhz. 3. when v dda and v ssa pins are not available on the pinout, the adc refers to v dd and v ss. 4. any added external serial resistor will downgrade the adc accuracy (espec ially for resistance greater than 10k ? ). data based on characterization resu lts, not tested in production. 5. the stabilization time of the a/d converter is masked by the first t load . the first conversion after the enable is then always valid. figure 64. typical application with adc symbol parameter conditions min typ 1) max unit f adc adc clock frequency 2) 4mhz v ain conversion voltage range 3) v ssa v dda v r ain external input resistor v dd = 5v, f adc =4mhz 8k 4) ? v dd = 3.3v, f adc =4mhz 7k 4) 2.7v v dd 5.5v, f adc =2mhz 10k 4) 2.4v v dd 2.7v, f adc =1mhz tbd 4) c adc internal sample and hold capacitor 3 pf t stab stabilization time after adc enable f cpu =8mhz, f adc =4mhz 0 5) s t adc conversion time (sample+hold) 3.5 - sample capacitor loading time - hold conversion time 4 10 1/f adc ainx st7liteusx v dd i l 1 a v t 0.6v v t 0.6v c adc v ain r ain 10-bit a/d conversion 1 st7liteusx 89/108 adc characteristics (cont?d) adc accuracy with v dd = 3.3v to 5.5v note: 1. data based on characterization result s over the whole temperature range. adc accuracy with v dd = 2.7v to 3.3v note: 1. data based on characterization result s over the whole temperature range. adc accuracy with v dd = 2.4v to 2.7v note: 1. data based on characterization results at a te mperature range 25 c. symbol 1) parameter conditions typ max unit |e t | total unadjusted error f cpu =8mhz, f adc =4mhz 1) 2.1 5.0 lsb |e o | offset error 0.2 2.5 |e g | gain error 0.3 1.5 |e d | differential linear ity error 1.9 3.5 |e l | integral linearity error 1.9 4.5 symbol 1) parameter conditions typ max unit |e t | total unadjusted error f cpu =4mhz, f adc =2mhz 1) 2.0 3.0 lsb |e o | offset error 0.1 1.5 |e g | gain error 0.4 1.4 |e d | differential linearity error 1.8 2.5 |e l | integral linearity error 1.7 2.5 symbol 1) parameter conditions typ max unit |e t | total unadjusted error f cpu =2mhz, f adc =1mhz 1) 2.2 3.5 lsb |e o | offset error 0.5 1.5 |e g | gain error 0.5 1.5 |e d | differential linearity error 1.8 2.5 |e l | integral linearity error 1.8 2.5 1 st7liteusx 90/108 adc characteristics (cont?d) figure 65. adc accuracy characteristics e o e g 1lsb ideal 1lsb ideal v dd v ss ? 1024 ------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum devi- ation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ide- al one. e l =integral linearity error: maximum devi- ation between any actual transition and the end point correlation line. digital result adcdr 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v dd v ss 1 st7liteusx 91/108 13 package characteristics in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level in- terconnect. the category of second level inter- connect is marked on the package and on the in- ner box label, in comp liance with jedec standard jesd97. the maximum ratings related to solder- ing conditions are also marked on the inner box la- bel. ecopack is an st tra demark. ecopack speci- fications are available at: www.st.com. 13.1 package mechanical data figure 66. 8-lead very thin fine pitch dual flat no-lead package dim. mm inches 1) note 1. values in inches are converted from mm and rounded to 3 decimal digits. min typ max min typ max a 0.80 0.90 1.00 0.031 0.035 0.039 a1 0.00 0.02 0.05 0.000 0.001 0.002 a3 0.20 0.008 b 0.25 0.30 0.35 0.010 0.012 0.014 d 4.50 0.177 d2 3.50 3.65 3.75 0.138 0.144 0.148 e 3.50 0.138 e2 1.96 2.11 2.21 0.077 0.083 0.087 e 0.80 0.031 l 0.30 0.40 0.50 0.012 0.016 0.020 number of pins n 8 a1 a3 (d/2 x e/2) d e a b e (d/2 x e/2) l e2 top view side view bottom view d2 index area index area 1 st7liteusx 92/108 package characteristics (cont?d) figure 67. 8-pin plastic small outline package, 150-mil width figure 68. 8-pin plastic dual in-line package, 300-mil width dim. mm inches 1) min typ max min typ max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 a2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.007 0.010 d 4.80 5.00 0.189 0.197 e 3.80 4.00 0.150 0.158 e 1.27 0.050 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 0d 8d l 0.40 1.27 0.016 0.050 number of pins n 8 note 1. values in inches are converted from mm and rounded to 3 decimal digits. d b a1 a h x 45 a2 h e e l c dim. mm inches 1) min typ max min typ max a 5.33 0.210 a1 0.38 0.015 a2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 b3 0.76 0.99 1.14 0.030 0.039 0.045 c 0.20 0.25 0.36 0.008 0.010 0.014 d 9.02 9.27 10.16 0.355 0.365 0.400 d1 0.13 0.005 e 2.54 0.100 eb 10.92 0.430 e 7.62 7.87 8.26 0.300 0.310 0.325 e1 6.10 6.35 7.11 0.240 0.250 0.280 l 2.92 3.30 3.81 0.115 0.130 0.150 number of pins n 8 note 1. values in inches are converted from mm and rounded to 3 decimal digits. 8 1 4 a l b2 e d b d1 e1 b3 eb 5 a2 e c a1 d 1 st7liteusx 93/108 package characteristics (cont?d) figure 69. 16-pin plastic dual in-line package, 300-mil width table 21. thermal characteristics notes: 1. the maximum chip-junction temperature is based on technology characteristics. 2. the maximum power dissipation is obtained from the formula p d = (t j -t a ) / r thja . the power dissipation of an application can be defined by the user wi th the formula: p d =p int +p port where p int is the chip internal power (i dd x v dd ) and p port is the port power dissipation depending on the ports used in the application. dim. mm inches 1) min typ max min typ max a 5.33 0.210 a1 0.38 0.015 a2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 b3 0.76 0.99 1.14 0.030 0.039 0.045 c 0.20 0.25 0.36 0.008 0.010 0.014 d 18.67 19.18 19.69 0.735 0.755 0.775 d1 0.13 0.005 e 2.54 0.100 e 7.62 7.87 8.26 0.300 0.310 0.325 e1 6.10 6.35 7.11 0.240 0.250 0.280 l 2.92 3.30 3.81 0.115 0.130 0.150 eb 10.92 0.430 number of pins n 16 note 1. values in inches are converted from mm and rounded to 3 decimal digits. c e e1 eb l a a2 a1 e b b2 b3 d1 d symbol ratings value unit r thja package thermal resistance (junction to ambient) dip8 82 c/w so8 130 dfn8 (on 4-layer pcb) dfn8 (on 2-layer pcb) 50 106 t jmax maximum junction temperature 1) 150 c p dmax power dissipation 2) dip8 300 mw so8 180 dfn8 (on 4-layer pcb) 500 dfn8 (on 2-layer pcb) 250 1 st7liteusx 94/108 13.2 soldering information in accordance with the rohs european directive, all stmicroelectronics packages have been con- verted to lead-free technology, named eco- pack tm . ecopack tm packages are qualified according to the jedec std-020c compliant soldering profile. detailed information on the stmicroelectronics ecopack tm transition program is available on www.st.com/stonline/le adfree/, with specific technical application notes covering the main technical aspects related to lead-free conversion (an2033, an2034, an2035, an2036). backward and forward compatibility: the main difference between pb and pb-free sol- dering process is the temperature range. ? ecopack tm lqfp, sdip, so and dfn8 pack- ages are fully compatible with lead (pb) contain- ing soldering process (see application note an2034) ? lqfp, sdip and so pb-packages are compati- ble with lead-free soldering process, neverthe- less it's the customer's duty to verify that the pb- packages maximum temperature (mentioned on the inner box label) is compatible with their lead- free soldering temperature. table 22. soldering compatibility (wave and reflow soldering process) * assemblers must verify that the pb-package maximum temperature (mentioned on the inner box label) is compatible with their l ead-free soldering process. package plating material devices pb solder paste pb-free solder paste sdip & pdip sn (pure tin) yes yes * dfn8 sn (pure tin) yes yes * tqfp and so nipdau (nickel-palladium-gold) yes yes * 1 st7liteusx 95/108 14 device configuration and ordering information each device is available for production in user pro- grammable versions (flash) as well as in factory coded versions (fastrom). st7pliteus2 and st7pliteus5 devices are factory advanced service technique rom (fas- trom) versions: they are factory-programmed xflash devices. st7fliteus2 and st7fliteus5 xflash devices are shipped to customers with a default program memory content (ffh). the fastrom factory coded parts contain the code supplied by the customer. this implies that flash devices have to be configured by the cus- tomer using the option bytes while the fastrom devices are factory-configured. 14.1 option bytes the two option bytes allow the hardware configu- ration of the microcontroller to be selected. the option bytes can be accessed only in pro- gramming mode (for example using a standard st7 programming tool). option byte 1 bit 7:6 = cksel[1:0] start-up clock selection. this bit is used to select the startup frequency. by default, the internal rc is selected. bit 5 = reserved, must always be 1. bit 4 = reserved, must always be 0. bits 3:2 = lvd[1:0] low voltage detection selec- tion these option bits enable the lvd block with a se- lected threshold as shown in table 23 . table 23. lvd threshold configuration bit 1 = wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) bit 0 = wdg halt watchdog reset on halt this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode option byte 0 bits 7:4 = reserved , must always be 1. bit 3 = reserved, must always be 0. bit 2 = sec0 sector 0 size definition this option bit indicates the size of sector 0 ac- cording to the following table. bit 1 = fmp_r read-out protection readout protection, when selected provides a pro- tection against program memory content extrac- tion and against write access to flash memory. erasing the option bytes when the fmp_r option is selected will cause the whole memory to be erased first, and the device can be reprogrammed. refer to section 4.5 and the st7 flash program- ming reference manual for more details. 0: read-out protection off 1: read-out protection on bit 0 = fmp_w flash write protection this option indicates if the flash program mem- ory is write protected. warning: when this option is selected, the pro- gram memory (and the option bit itself) can never be erased or programmed again. 0: write protection off 1: write protection on configuration cksel1 cksel0 internal rc as startup clock 0 0 awu rc as a startup clock 0 1 reserved 1 0 external clock on pin pa5 1 1 configuration lvd1 lvd0 lvd off 1 1 highest voltage threshold 1 0 medium voltage threshold 0 1 lowest voltage threshold 0 0 sector 0 size sec0 0.5k 0 1k 1 1 st7liteusx 96/108 option bytes (cont?d) option byte 0 70 option byte 1 70 reserved sec 0 fmp r fmp w cks el1 cks el0 res res lvd1 lvd0 wdg sw wdg halt default value 1111000000101111 1 st7liteusx 97/108 14.2 ordering information customer code is made up of the fastrom con- tents and the list of the selected options (if any). the fastrom contents are to be sent on dis- kette, or by electronic means, with the s19 hexa- decimal file generated by the development tool. all unused bytes must be set to ffh. the selected op- tions are communicated to stmicroelectronics us- ing the correctly completed option list append- ed. refer to application note an1635 for information on the counter listing returned by st after code has been transferred. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. table 24. supported part numbers part number program memory (bytes) ram (bytes) adc temp. range package conditioning st7fliteus2b6 1k flash 128 - -40c +85c dip8 tube st7fliteus2m6 - so8 tube st7fliteus2m6tr - so8 tape & reel st7fliteus2u6tr - dfn8 tape & reel st7fliteus5b6 1k flash 128 10-bit -40c +85c dip8 tube st7fliteus5m6 10-bit so8 tube st7fliteus5m6tr 10-bit so8 tape & reel st7fliteus5u6 10-bit dfn8 tray st7fliteus5u6tr 10-bit dfn8 tape & reel st7fliteusicd 1k flash 128 - -40c +125c dip16 1) tube st7pliteus2b6 1k fastrom 128 - -40c +85c dip8 tube st7pliteus2m6 - so8 tube st7pliteus2m6tr - so8 tape & reel st7pliteus2u6tr - dfn8 tape & reel st7pliteus5b6 1k fastrom 128 10-bit -40c +85c dip8 tube st7pliteus5m6 10-bit so8 tube st7pliteus5m6tr 10-bit so8 tape & reel st7pliteus5u6 10-bit dfn8 tray ST7PLITEUS5U6TR 10-bit dfn8 tape & reel st7fliteus2b3 1k flash 128 - -40c +125c dip8 tube st7fliteus2m3 - so8 tube st7fliteus2m3tr - so8 tape & reel st7fliteus2u3tr - dfn8 tape & reel st7fliteus5b3 1k flash 128 10-bit -40c +125c dip8 tube st7fliteus5m3 10-bit so8 tube st7fliteus5m3tr 10-bit so8 tape & reel st7fliteus5u3 10-bit dfn8 tray st7fliteus5u3tr 10-bit dfn8 tape & reel 1 st7liteusx 98/108 note: 1. for development or tool prot otyping purposes only, not orderable in production quantities. st7pliteus2b3 1k fastrom 128 - -40c +125c dip8 tube st7pliteus2m3 - so8 tube st7pliteus2m3tr - so8 tape & reel st7pliteus2u3tr - dfn8 tape & reel st7pliteus5b3 1k fastrom 128 10-bit -40c +125c dip8 tube st7pliteus5m3 10-bit so8 tube st7pliteus5m3tr 10-bit so8 tape & reel st7pliteus5u3 10-bit dfn8 tray st7pliteus5u3tr 10-bit dfn8 tape & reel contact st sales office for product availability 1 st7liteusx 99/108 st7liteus fastrom microcontroller option list (last update: january 2007) customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone no . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference fastrom code*: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . *fastrom code name is assigned by stmicroelectronics. fastrom code must be sent in .s19 format . .hex extension cannot be processed. device type/memory size/pac kage (check only one option): conditioning (check only one option): special marking: [ ] no [ ] yes "_ _ _ _ _ _ _ _ " authorized characters are letters, di gits, '.', '-', '/ ' and spaces only. maximum character count: pdip8/so8/dfn8 (8 char. max) : _ _ _ _ _ _ _ _ temperature range: [ ] -40c to +85c [ ] -40c to +125c clock source selection: [ ] external clock [ ] awu rc oscillator [ ] internal rc oscillator sector 0 size: [ ] 0.5k [ ] 1k readout protection: [ ] disabled [ ] enabled flash write protection [ ] disabled [ ] enabled lvd reset [ ] disabled [ ] highest threshold [ ] medium threshold [ ] lowest threshold watchdog selection: [ ] software ac tivation [ ] hard ware activation watchdog reset on halt: [ ] disabled [ ] enabled comments : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply operating range in the applic ation: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . important note: not all configurations are available. see section 14.1 on page 95 for authorized option byte combinations. please download the latest versi on of this option list from: http://www.st.com/mcu > downloads > st7 microcontrollers > option list --------------------------------- fastrom device: --------------------------------- | | | | ----------------------------------------- 1k fastrom ----------------------------------------- pdip8: || [ ] so8: || [ ] dfn8: || [ ] dip package: [ ] tube so package: [ ] tape & reel [ ] tube dfn package: [ ] tape & reel [ ] tray (for st7pliteus5u6 and st7pliteus5u3 only) 1 st7liteusx 100/108 14.3 development tools development tools for the st7 microcontrollers in- clude a complete range of hardware systems and software tools from stmicroelectronics and third- party tool suppliers. the range of tools includes solutions to help you evaluate microcontroller pe- ripherals, develop and debug your application, and program your microcontrollers. 14.3.1 starter kits st offers complete, affordable starter kits . starter kits are complete, affordable hardware/software tool packages that include features and samples to help you quickly start developing your applica- tion. 14.3.2 development and debugging tools application development for st7 is supported by fully optimizing c compilers and the st7 assem- bler-linker toolchain, which are all seamlessly in- tegrated in the st7 integrated development envi- ronments in order to facilitate the debugging and fine-tuning of your application. the cosmic c compiler is available in a free version that outputs up to 16kbytes of code. the range of hardware tools includes full-featured st7-emu3 series emulators, cost effective st7- dvp3 series emulators and the low-cost rlink in-circuit debugger/programmer. these tools are supported by the st7 toolset from stmicroelec- tronics, which includes the stvd7 integrated de- velopment environment (ide) with high-level lan- guage debugger, editor, project manager and inte- grated programming interface. 14.3.3 programming tools during the development cycle, the st7-dvp3 and st7-emu3 series emulators and the rlink pro- vide in-circuit programmi ng capability for program- ming the flash microcontroller on your application board. st also provides a low- cost dedicated in-circuit programmer, the st7-stick , as well as st7 socket boards which provide all the sockets re- quired for programming any of the devices in a specific st7 sub-family on a platform that can be used with any tool with in-circuit programming ca- pability for st7. for production programming of st7 devices, st?s third-party tool partners also provide a complete range of gang and automated programming solu- tions, which are ready to integrate into your pro- duction environment. 14.3.4 order codes for development and programming tools table 25 below lists the ordering codes for the st7liteusx development and programming tools. for additional ordering codes for spare parts and accessories, refer to the online product selec- tor at www.st.com/mcu. 14.3.5 order codes for st7liteusx development tools table 25. development tool order codes for the st7liteusx family notes: 1. available from st or from raisonance, www.raisonance.com 2. usb connection to pc 3. add suffix /eu, /uk or /us fo r the power supply for your region 4. includes connection kit for dip16/so16 only. see ?how to order an emu or dvp? in st product and tool selection guide for connection kit ordering information 5. parallel port connection to pc supported products in-circuit debugger, rlink series 1) emulator programming tool starter kit without demo board starter kit with demo board dvp series emu series in-circuit programmer st socket boards and epbs st7fliteus2 st7fliteus5 stx-rlink 2) stflite- sk/rais 2) st7mdt10- dvp3 4) st7mdt10- emu3 stx-rlink st7-stick 3)5) st7sb10- su0 3) 1 st7liteusx 101/108 14.4 st7 application notes table 26. st7 application notes identification description application examples an1658 serial numbering implementation an1720 managing the read-out protection in flash microcontrollers an1755 a high resolution/precision thermometer using st7 and ne555 an1756 choosing a dali implementation strategy with st7dali an1812 a high precision, low cost, single supply adc for positive and negative in- put voltages example drivers an 969 sci communication between st7 and pc an 970 spi communication between st7 and eeprom an 971 i2c communication between st7 and m24cxx eeprom an 972 st7 software spi master communication an 973 sci software communication with a pc using st72251 16-bit timer an 974 real time clock with st7 timer output compare an 976 driving a buzzer through st7 timer pwm function an 979 driving an analog keyboard with the st7 adc an 980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 universal serial bus microcontroller an1041 using st7 pwm signal to generate analog output (sinuso?d) an1042 st7 routine for i2c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 s/w implementation of i2c bus master an1046 uart emulation software an1047 managing reception errors with the st7 sci peripherals an1048 st7 software lcd driver an1078 pwm duty cycle switch implementing true 0% & 100% duty cycle an1082 description of the st72141 motor control peripherals registers an1083 st72141 bldc motor control software and flowchart example an1105 st7 pcan peripheral driver an1129 pwm management for bldc motor drives using the st72141 an1130 an introduction to sensorless brushless dc motor drive applications with the st72141 an1148 using the st7263 for designing a usb mouse an1149 handling suspend mode on a usb mouse an1180 using the st7263 kit to implement a usb game pad an1276 bldc motor start routine for the st72141 microcontroller an1321 using the st72141 motor control mcu in sensor mode an1325 using the st7 usb low-speed firmware v4.x an1445 emulated 16-bit slave spi an1475 developing an st7265x mass storage application an1504 starting a pwm signal directly at high level using the st7 16-bit timer an1602 16-bit timing operations using st7262 or st7263b st7 usb mcus an1633 device firmware upgrade (dfu) implementation in st7 non-usb applications an1712 generating a high resolution sinewave using st7 pwmart an1713 smbus slave driver for st7 i2c peripherals an1753 software uart using 12-bit art 1 st7liteusx 102/108 an1947 st7mc pmac sine wave motor control software library general purpose an1476 low cost power supply for home appliances an1526 st7flite0 quick reference note an1709 emc design for st microcontrollers an1752 st72324 quick reference note product evaluation an 910 performance benchmarking an 990 st7 benefits vs industry standard an1077 overview of enhanced can controllers for st7 and st9 mcus an1086 u435 can-do solutions for car multiplexing an1103 improved b-emf detection for low speed, low voltage with st72141 an1150 benchmark st72 vs pc16 an1151 performance comparison between st72254 & pc16f876 an1278 lin (local interconnect network) solutions product migration an1131 migrating applications from st72511/311/214/124 to st72521/321/324 an1322 migrating an application from st7263 rev.b to st7263b an1365 guidelines for migrating st72c254 applications to st72f264 an1604 how to use st7mdt1-train with st72f264 an2200 guidelines for migrating st7lite1x applications to st7flite1xb product optimization an 982 using st7 with ceramic resonator an1014 how to minimize the st7 power consumption an1015 software techniques for improving microcontroller emc performance an1040 monitoring the vbus signal for usb self-powered devices an1070 st7 checksum self-checking capability an1181 electrostatic discharge sensitive measurement an1324 calibrating the rc oscillator of the st7flite0 mcu using the mains an1502 emulated data eeprom with st7 hdflash memory an1529 extending the current & voltage capability on the st7265 vddf supply an1530 accurate timebase for low-cost st7 applications with internal rc oscilla- tor an1605 using an active rc to wakeup the st7lite0 from power saving mode an1636 understanding and minimizing adc conversion errors an1828 pir (passive infrared) detector using the st7flite05/09/superlite an1946 sensorless bldc motor control and bemf sampling methods with st7mc an1953 pfc for st7mc starter kit an1971 st7lite0 microcontrolled ballast programming and tools an 978 st7 visual develop software key debugging features an 983 key features of the cosmic st7 c-compiler package an 985 executing code in st7 ram an 986 using the indirect addressing mode with st7 an 987 st7 serial test controller programming an 988 starting with st7 assembly tool chain an1039 st7 math utility routines table 26. st7 application notes identification description 1 st7liteusx 103/108 an1071 half duplex usb-to-serial bridge using the st72611 usb microcontroller an1106 translating assembly code from hc05 to st7 an1179 programming st7 flash microcontrollers in remote isp mode (in-situ pro- gramming) an1446 using the st72521 emulator to debug an st72324 target application an1477 emulated data eeprom with xflash memory an1527 developing a usb smartcard reader with st7scr an1575 on-board programming methods for xflash and hdflash st7 mcus an1576 in-application programming (iap) drivers for st7 hdflash or xflash mcus an1577 device firmware upgrade (dfu) implementation for st7 usb applications an1601 software implementation for st7dali-eval an1603 using the st7 usb device firmware upgrade development kit (dfu-dk) an1635 st7 customer rom code release information an1754 data logging program for testing st7 applications via icc an1796 field updates for flash based st7 applications using a pc comm port an1900 hardware implementation for st7dali-eval an1904 st7mc three-phase ac induction motor control software library an1905 st7mc three-phase bldc motor control software library system optimization an1711 software techniques for compensating st7 adc errors an1827 implementation of sigma-delta adc with st7flite05/09 an2009 pwm management for 3-phase bldc motor drives using the st7fmc an2030 back emf detection during pwm on time by st7mc table 26. st7 application notes identification description 1 st7liteusx 104/108 15 known limitations 15.1 limitations in user mode 15.1.1 flash memory access when exiting from halt mode description when exiting from halt mode, the cpu starts to run after 64 cycles. however, to work properly and to be accessed safely, the flash memory needs a delay of 42 s. this problem occurs only with a cpu frequency from 2mhz to 8mhz (i.e. with a wake-up time from halt mode respectively from 32s to 8s). this limitation is not present in the following cases: ? at power-on (as an additional delay of 34s is al- ways applied) ? for internal reset as flash memory cells are not stopped. workaround the cpu frequency must be set by software at 1mhz before entering halt mode. when the cpu exits from halt mode by an exter- nal reset, the reset pulse of at least 42s must be applied. 15.1.2 spurious avd interrupt when avd switches on and lvd is off description if lvd is selected off by the option bytes, when the avd is turned on by selecting one of the three levels with the avdthcr register, a spurious avd interrupt is generated. workaround in the application using an avd threshold with lvd off, the user can insure that the avd inter- rupt is not a spurious one by checking if avdf is on when entering the avd interrupt subroutine. 15.2 limitation s in icc mode these limitations can concern icp (programming) and/or icd (debugging) and a workaround (when available) should be implemented in any program- ming or debugging tool, as described in the follow- ing sections. 15.2.1 spurious lvd reset after programming the option bytes description when programming the lvd option from off to on in icc mode with op tion bytes enabled (38- pulse mode) and if the avd is off, a spurious re- set is generated and icc communication is lost. workaround at the user level, using the icc mode with option bytes disabled (35-pulse mode), no spurious reset is generated. at the programming tool designer level, either by generating a reset after or by setting the avd on before programming the option bytes, a spurious lvd reset is avoided. 15.2.2 in-circuit programming of devices previously programmed with hardware watchdog option description in-circuit programming of devices configured with hardware watchdog (wdgsw bit in option byte 1 programmed to 0) requires certain precautions (see below). in-circuit programming uses icc mode. in this mode, the hardware watchdog is not automatically deactivated as one might expect. as a conse- quence, internal resets are generated by the watchdog, thus preventing programming. the device factory configuration is software watchdog so this issue is not seen with devices that are programmed for the first time. for the same reason, devices programmed by the user with the software watchdog option are not impact- ed. the only devices impacted are those that have previously been programmed with the hardware watchdog option. workaround devices configured with hardware watchdog must be programmed using a specific program- ming mode that ignores the option byte settings. in this mode, an external clock, normally provided by the programming tool, has to be used. in st tools, this mode is called "i cp options disabled". sockets on st programming tools are controlled using "icp options disabled" mode. devices can therefore be reprogrammed by plugging them in the st programming board socket, whatever the watchdog configuration. 1 st7liteusx 105/108 when using third-party tools, please refer the manufacturer's documentation to check how to ac- cess specific programming modes. if a tool does not have a mode that ignores the option byte set- tings, devices programmed with the hardware watchdog option cannot be reprogrammed using this tool. 15.2.3 in-circuit debugging with hardware watchdog in-circuit debugging is im pacted in the same way as in-circuit programming by the activation of the hardware watchdog in icc mode. please refer to section 15.2.2 . 1 st7liteusx 106/108 16 revision history date revision main changes 06-feb-06 1 initial release 18-apr-06 2 removed references to 3% rc added note below figure 4 on page 6 modified presentation of section 4.3.1 on page 11 added notes to section 6.1 on page 17 (above figure 9 ), replaced 8-bit calibration value to 10-bit calibration value and changed application note reference (an2326 instead of an1324) modifed table 5, ?clock register map and reset values,? on page 20 and added bit 1 in the description of ckcntcsr register modified figure 10 on page 21 (added ckcntcsr register) added note 2 to eicrx description on page 27 modified caution in section 7.2 on page 25 replaced v it+(lvd) by v it+(lvd) in section 7.4.2.1 on page 29 modified lvdrf bit description in section 7.4.4 on page 31 replaced ?oscillator? by ?main os cillator? in the second paragraph of section 8.4.2 on page 36 added note 1 to figure 23 on page 36 and added note 5 to figure 24 on page 36 modified section 8.5 on page 37 replaced bit 1 by bit 2 for awuf bit in section 8.5.1 on page 40 modified section 9.1 on page 41 modified section 9.2.1.1 on page 41 updated section 9.5 on page 45 modified section 12.3.2 on page 70 modified section 12.3.3 on page 70 modified section 12.3.4 on page 71 modified section 12.3.5 on page 71 modified section 12.4.1 on page 73 modified section 12.4.2 on page 75 modified section 12.5.2 on page 76 modified section 12.8.1 on page 81 modified section 12.8.2 on page 82 modified section 12.9.1 on page 86 modified section 12.10 on page 88 added figure 48 on page 82 modified figure 62 on page 87 removed emc protection circuitry in figure 63 on page 87 (device works correctly with- out these components) added ecopack text in section 13 on page 91 modified first paragraph in section 13.2 on page 94 modified table 24 on page 97 modified conditioning opt ion in option list on page 99 modified ?development tools? on page 100 added section 14.4 on page 101 added ?known limitations? on page 104 added erratasheet at the end of the document revision history continued overleaf ... 1 st7liteusx 107/108 18-sep-06 3 modified description of avd[1:0] bi ts in the avdtrh register in section 7.4.4 on page 31 modified description of cntr[11:0] bits in section 10.2.6 on page 54 modified values in section 12.2.2 on page 68 lvd and avd tables updated, section 12.3.2 , section 12.3.3 and section 12.3.4 on page 71 internal rc oscillat or data modified in section 12.3.5.1 and new table added section 12.3.5.2 on page 72 typical data in section 12.4.2 on page 75 (on chip peri pherals) modified emc characteristics updated, section 12.7 on page 78 r pu data corrected in section 12.8.1 on page 81 including additional notes output driving cu rrent table updated, section 12.8.2 on page 82 r on data corrected in section 12.9.1 on page 86 modified adc accuracy tables in section 12.10 on page 89 ?known limitations? on page 104 updated errata sheet removed from document notes modified for low voltage detector section 7.4.1 on page 28 notes updated in section 4.4 on page 12 (icc interface) thermal characteristics table updated, table 21 on page 93 modified option list on page 99 modified ?development tools? on page 100 modified text in section 15.2 on page 104 26-jan-07 4 added -40c to 125c temperature range added caution to section 6.3.1 on page 22 modified note on ei4 in table 7 , ?interrupt mapping,? on page 26 added note 3 to ?external interrupt control register 2 (eicr2)? on page 27 added a note to lvdrf in section 7.4.4 on page 31 added figure 41 on page 72 and figure 40 on page 72 modified section 12.3.2 on page 70 and section 12.3.3 on page 70 modified section 12.3.5 on page 71 updated section 12.4.1 on page 73 updated section 12.8.2 on page 82 modified r ain and adc accuracy tables in section 12.10 on page 88 modified table 25 on page 100 modified table 24 on page 97 modified option list on page 99 1 st7liteusx 108/108 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in mi litary, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from 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